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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.Bob Wilson2010-12-231-0/+3
| | | | | | | | If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. llvm-svn: 122521
* Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson2010-12-211-5/+103
| | | | | | | | | | | Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. llvm-svn: 122319
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-9/+9
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Add some missing entries in ARMTargetLowering::getTargetNodeName.Bob Wilson2010-12-181-0/+5
| | | | llvm-svn: 122111
* Don't handle -arm-long-calls in fast isel for now.Eric Christopher2010-12-151-1/+1
| | | | llvm-svn: 121919
* bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663Evan Cheng2010-12-141-0/+20
| | | | llvm-svn: 121746
* Generalize BFI isel lowering a bit.Evan Cheng2010-12-131-29/+35
| | | | llvm-svn: 121714
* (or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == ↵Evan Cheng2010-12-111-7/+28
| | | | | | #shamt. rdar://8752056 llvm-svn: 121606
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-071-1/+1
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* Fix and re-enable tail call optimization of expanded libcalls.Evan Cheng2010-12-011-1/+4
| | | | llvm-svn: 120622
* Enable sibling call optimization of libcalls which are expanded duringEvan Cheng2010-11-301-19/+54
| | | | | | | | | | | legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 llvm-svn: 120501
* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-281-7/+96
| | | | llvm-svn: 120236
* Add entry in getTargetNodeName() for ARMISD::VBICIMM.Bob Wilson2010-11-281-1/+2
| | | | llvm-svn: 120233
* Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson2010-11-231-13/+109
| | | | | | | We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. llvm-svn: 120034
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-51/+51
| | | | llvm-svn: 119990
* These instructions are thumb2 only.Evan Cheng2010-11-191-1/+1
| | | | llvm-svn: 119793
* Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on ↵Tanya Lattner2010-11-181-1/+2
| | | | | | | | illegal types (vector should be split first). Added test case. llvm-svn: 119749
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-2/+4
| | | | llvm-svn: 119740
* Split up ARM LowerShift function.Bob Wilson2010-11-181-26/+33
| | | | | | | | | | | | | This function was being called from two different places for completely unrelated reasons. During type legalization, it was called to expand 64-bit shift operations. During operation legalization, it was called to handle Neon vector shifts. The vector shift code was not written to check for illegal types, since it was assumed to be only called after type legalization. Fixed this by splitting off the 64-bit shift expansion into a separate function. I don't have a particular testcase for this; I just noticed it by inspection. llvm-svn: 119738
* Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build ↵Nate Begeman2010-11-101-2/+2
| | | | | | vector with 2 elts llvm-svn: 118720
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-2/+2
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 llvm-svn: 118642
* Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach2010-11-091-4/+4
| | | | | | help in MC'izing the references that use them. llvm-svn: 118633
* Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson2010-11-081-1/+32
| | | | llvm-svn: 118453
* Disallow the certain NEON modified-immediate forms when generating vorr or vbic.Owen Anderson2010-11-051-7/+14
| | | | llvm-svn: 118300
* Add codegen and encoding support for the immediate form of vbic.Owen Anderson2010-11-051-1/+34
| | | | llvm-svn: 118291
* Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng2010-11-041-10/+11
| | | | | | immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
* Covert VORRIMM to be produced via early target-specific DAG combining, ↵Owen Anderson2010-11-031-31/+26
| | | | | | | | rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. llvm-svn: 118204
* Add support for code generation of the one register with immediate form of vorr.Owen Anderson2010-11-031-0/+29
| | | | | | | We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. llvm-svn: 118201
* Check for extractelement with a variable operand for the element number.Bob Wilson2010-11-031-10/+15
| | | | | | For NEON we had been assuming this was always an immediate constant. llvm-svn: 118175
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-1/+1
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-031-4/+29
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-031-0/+5
| | | | llvm-svn: 118152
* NEON does not support truncating vector stores. Radar 8598391.Bob Wilson2010-11-011-0/+4
| | | | llvm-svn: 117940
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-301-12/+20
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.Evan Cheng2010-10-291-3/+7
| | | | | | - Compute CopyToReg use operand latency correctly. llvm-svn: 117674
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-291-0/+34
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Fix compiler warnings about signed/unsigned comparisons.Bob Wilson2010-10-271-2/+2
| | | | llvm-svn: 117511
* SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson2010-10-271-0/+55
| | | | | | | | | | | | | | | | | | | elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482
* Enable ARM fastcc.Evan Cheng2010-10-231-5/+1
| | | | llvm-svn: 117194
* Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by ↵Evan Cheng2010-10-221-12/+22
| | | | | | -arm-fastcc for now. llvm-svn: 117119
* Fix crash introduced in 116852. 8573915.Dale Johannesen2010-10-201-2/+3
| | | | llvm-svn: 116955
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-0/+11
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* Enable using vdup for vector constants which are splat ofDale Johannesen2010-10-191-32/+17
| | | | | | | integers by default, and remove the controlling flag, now that LICM will hoist such vdup's. 8003375. llvm-svn: 116852
* Don't mark argument value stores as immutable, as otherwise the post-RAJim Grosbach2010-10-151-1/+1
| | | | | | | scheduler may reorder loads from them before the stores and other such badness. PR8347. Patch by David Meyer llvm-svn: 116602
* Remove unused ARMISD::AND selection DAG node.Bob Wilson2010-10-151-1/+0
| | | | llvm-svn: 116566
* User proper libcall names & condcodes while compiling for ARM EABI.Anton Korobeynikov2010-09-281-6/+150
| | | | | | Patch by Evzen Muller! llvm-svn: 114991
* Add a command line option "-arm-strict-align" to disallow unaligned memoryBob Wilson2010-09-281-9/+1
| | | | | | accesses for ARM targets that would otherwise allow it. Radar 8465431. llvm-svn: 114941
* Enable code placement optimization pass for ARM.Evan Cheng2010-09-241-7/+1
| | | | llvm-svn: 114746
* Add support for ELF PLT references for ARM MC asm printing. Adding aJim Grosbach2010-09-221-4/+16
| | | | | | | | new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure there's a more straightforward way to get the printing difference captured. (i.e., x86 uses @PLT, ARM uses (PLT)). llvm-svn: 114613
* Change VDUPLANE DAG combiner to just return the result instead of callingBob Wilson2010-09-221-5/+3
| | | | | | | | CombineTo to avoid putting the result on the worklist. I don't think it makes much difference for now, but it might help someday as we add more DAG combine optimizations. llvm-svn: 114595
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