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* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-041-0/+32
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
* Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen2012-08-181-120/+0
| | | | | | | These nodes are no longer needed because the peephole pass can fold CMOV+AND into ANDCC etc. llvm-svn: 162179
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-151-14/+20
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-121-32/+0
| | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. llvm-svn: 161736
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-091-0/+32
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 161581
* Clean up formatting.Jim Grosbach2012-08-011-8/+0
| | | | llvm-svn: 161133
* Tidy up.Jim Grosbach2012-08-011-11/+4
| | | | llvm-svn: 161132
* Make some opcode tables static and const. Allows code to avoid making copies ↵Craig Topper2012-05-241-173/+219
| | | | | | to pass the tables around. llvm-svn: 157373
* Test commit.Tim Northover2012-04-261-2/+0
| | | | llvm-svn: 155626
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-1/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 llvm-svn: 154511
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-1/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 llvm-svn: 154505
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-8/+7
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-45/+37
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Remove unused variable.Duncan Sands2012-02-231-1/+0
| | | | llvm-svn: 151251
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-3/+115
| | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-2/+1
| | | | llvm-svn: 149961
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-101-1/+1
| | | | | | rdar://10663487 llvm-svn: 147876
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-211-3/+14
| | | | llvm-svn: 147069
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-141-6/+15
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-8/+19
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-1/+2
| | | | llvm-svn: 145450
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-291-1/+2
| | | | llvm-svn: 145442
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-9/+33
| | | | llvm-svn: 143369
* Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen2011-10-271-1/+1
| | | | | | | Previously, we were only setting the alignment bits on over-aligned loads and stores. llvm-svn: 143160
* ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach2011-10-271-0/+4
| | | | llvm-svn: 143158
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-8/+34
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Fix misc warnings. Patch by Joe Abbey.Eli Friedman2011-10-181-1/+0
| | | | llvm-svn: 142332
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-101-0/+66
| | | | llvm-svn: 141591
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-101-66/+0
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* Disable ABS optimization for Thumb1 target, we don't have necessary ↵Anton Korobeynikov2011-10-081-0/+3
| | | | | | instructions there. llvm-svn: 141481
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-071-0/+63
| | | | | | Patch by Ana Pazos! llvm-svn: 141365
* Always merge profitable shifts on A9, not just when they have a single use.Cameron Zwarich2011-10-051-6/+2
| | | | llvm-svn: 141248
* Remove a check from ARM shifted operand isel helper methods, which were blockingCameron Zwarich2011-10-051-10/+0
| | | | | | | | merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. llvm-svn: 141247
* Add braces around something that throws me for a loop.Cameron Zwarich2011-10-051-1/+2
| | | | llvm-svn: 141173
* There is no point in setting out-parameters for a ComplexPattern function whenCameron Zwarich2011-10-051-1/+0
| | | | | | it returns false, at least as far as I could tell by reading the code. llvm-svn: 141172
* Also match negative offsets for addrmode3 and addrmode5.Jakob Stoklund Olesen2011-09-231-2/+2
| | | | | | | | Math is hard, and isScaledConstantInRange() always returned false for negative constants. It was doing unsigned division of negative numbers before casting back to signed. llvm-svn: 140425
* Tidy up a few 80 column violations.Jim Grosbach2011-09-131-4/+4
| | | | llvm-svn: 139636
* When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ↵Owen Anderson2011-08-311-1/+8
| | | | | | | | need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. <rdar://problem/10046188> llvm-svn: 138885
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-311-7/+13
| | | | llvm-svn: 138868
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-311-0/+32
| | | | llvm-svn: 138845
* addrmode_imm12 and addrmode2_offset encode their immediate values ↵Owen Anderson2011-08-291-4/+28
| | | | | | differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. llvm-svn: 138758
* Fix ARM codegen breakage caused by r138653.Owen Anderson2011-08-261-6/+15
| | | | llvm-svn: 138657
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-4/+4
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-2/+3
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* ARM refactor indexed store instructions.Jim Grosbach2011-08-051-2/+5
| | | | | | | | | | Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-2/+4
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-13/+40
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Fix test failures caused by my so_reg refactoring.Owen Anderson2011-07-221-2/+2
| | | | llvm-svn: 135785
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-11/+9
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
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