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* Change VST1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-9/+21
| | | | | | | of D registers. Add a separate VST1q instruction with a Q register source operand for use by storeRegToStackSlot. llvm-svn: 99265
* Change VLD1 instructions for loading Q register values to operate on pairsBob Wilson2010-03-231-10/+21
| | | | | | | of D registers. Add a separate VLD1q instruction with a Q register destination operand for use by loadRegFromStackSlot. llvm-svn: 99261
* Rename some VLD1/VST1 instructions to match the implementation, i.e., theBob Wilson2010-03-221-4/+4
| | | | | | | corresponding NEON instructions, instead of operation they are currently used for. llvm-svn: 99189
* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-53/+35
| | | | | | | with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
* Rename some instructions for consistency and sanity: use "_UPD" suffix forBob Wilson2010-03-201-20/+36
| | | | | | | | load/stores with address register writeback, and use "odd" suffix to distinguish instructions to access odd numbered registers (instead of "a" and "b"). No functional changes. llvm-svn: 99066
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-161-28/+46
| | | | llvm-svn: 98692
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-161-46/+28
| | | | | | | optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. llvm-svn: 98683
* Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner2010-03-021-7/+0
| | | | | | | | | | | | DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) llvm-svn: 97555
* Split SelectionDAGISel::IsLegalAndProfitableToFold toEvan Cheng2010-02-151-1/+3
| | | | | | | | IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use. This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses. llvm-svn: 96255
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-3/+3
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Fix r93758. Use isel patterns instead of c++ selection code to select rbit ↵Evan Cheng2010-01-191-6/+0
| | | | | | and make sure we pick different instructions for ARM vs. Thumb2. llvm-svn: 93829
* Patch by David Conrad:Jim Grosbach2010-01-181-0/+6
| | | | | | | "On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction sequence it is now." llvm-svn: 93758
* Fix an off-by-one error that caused the chain operand to be dropped from NeonBob Wilson2010-01-171-2/+2
| | | | | | vector load-lane and store-lane instructions. llvm-svn: 93673
* Change SelectCode's argument from SDValue to SDNode *, to make it moreDan Gohman2010-01-051-163/+158
| | | | | | | | | clear what information these functions are actually using. This is also a micro-optimization, as passing a SDNode * around is simpler than passing a { SDNode *, int } by value or reference. llvm-svn: 92564
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-4/+16
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* Add predicate operand to NEON instructions. Fix lots (but not all) 80 col ↵Evan Cheng2009-11-211-23/+50
| | | | | | violations in ARMInstrNEON.td. llvm-svn: 89542
* Fix codegen of conditional move of immediates. We were not making use of the ↵Evan Cheng2009-11-201-65/+127
| | | | | | immediate forms of cmov instructions at all. llvm-svn: 89423
* Refactor cmov selection code out to a separate function. No functionality ↵Evan Cheng2009-11-191-116/+122
| | | | | | change. llvm-svn: 89396
* 80 col violation.Evan Cheng2009-11-191-1/+2
| | | | llvm-svn: 89337
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-6/+6
| | | | llvm-svn: 86494
* Support alignment specifier for NEON vld/vst instructionsJim Grosbach2009-11-071-22/+27
| | | | llvm-svn: 86404
* Remove uninteresting and confusing debug output.Dan Gohman2009-11-051-2/+0
| | | | llvm-svn: 86149
* Prune unnecessary include.Bob Wilson2009-11-021-1/+0
| | | | llvm-svn: 85805
* Test commit. Added '.' to the comment line.Johnny Chen2009-10-271-1/+1
| | | | llvm-svn: 85255
* Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.Evan Cheng2009-10-221-1/+1
| | | | llvm-svn: 84813
* Match more patterns to movt.Evan Cheng2009-10-211-0/+37
| | | | llvm-svn: 84751
* Remove unused variables to fix build warning.Bob Wilson2009-10-141-3/+0
| | | | llvm-svn: 84144
* Refactor code to select NEON VST intrinsics.Bob Wilson2009-10-141-168/+112
| | | | llvm-svn: 84122
* Refactor code to select NEON VLD intrinsics.Bob Wilson2009-10-141-147/+109
| | | | llvm-svn: 84117
* More refactoring. NEON vst lane intrinsics can share almost all the code forBob Wilson2009-10-141-180/+32
| | | | | | vld lane intrinsics. llvm-svn: 84110
* Refactor code for selecting NEON load lane intrinsics.Bob Wilson2009-10-141-211/+122
| | | | llvm-svn: 84109
* More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsicsBob Wilson2009-10-131-36/+24
| | | | | | | by creating TargetConstants during instruction selection instead of during legalization. llvm-svn: 84042
* Revise ARM inline assembly memory operands to require the memory address toBob Wilson2009-10-131-8/+4
| | | | | | | be in a register. The previous use of ARM address mode 2 was completely arbitrary and inappropriate for Thumb. Radar 7137468. llvm-svn: 84022
* Fix method name in comment, per Bob Wilson.Sandeep Patel2009-10-131-1/+1
| | | | llvm-svn: 84017
* Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.Sandeep Patel2009-10-131-0/+64
| | | | llvm-svn: 84009
* Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.Bob Wilson2009-10-091-10/+52
| | | | llvm-svn: 83600
* Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-9/+49
| | | | llvm-svn: 83598
* Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-9/+47
| | | | llvm-svn: 83596
* Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-11/+73
| | | | | | Also fix some copy-and-paste errors in previous changes. llvm-svn: 83590
* Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-9/+64
| | | | llvm-svn: 83585
* Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-8/+57
| | | | llvm-svn: 83568
* Clean up some unnecessary initializations.Bob Wilson2009-10-081-2/+2
| | | | llvm-svn: 83566
* Clean up a comment (indentation was wrong).Bob Wilson2009-10-081-1/+2
| | | | llvm-svn: 83565
* Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83526
* Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83518
* Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83513
* Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83508
* Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83506
* Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83502
* Add codegen support for NEON vst4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-9/+61
| | | | llvm-svn: 83486
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