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path: root/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
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* Avoid creating two TargetLowering objects for each target.Dan Gohman2008-10-031-3/+1
* Cosmetic.Evan Cheng2008-09-181-3/+5
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-21/+27
* erect abstraction boundaries for accessing SDValue members, rename Val -> Nod...Gabor Greif2008-08-281-10/+10
* disallow direct access to SDValue::ResNo, provide a getter insteadGabor Greif2008-08-261-1/+1
* Move the point at which FastISel taps into the SelectionDAGISelDan Gohman2008-08-231-3/+3
* Simplify SelectRoot's interface, and factor out some common codeDan Gohman2008-08-211-1/+1
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-121/+121
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-2/+1
* Add explicit keywords.Dan Gohman2008-07-071-1/+1
* Split scheduling from instruction selection.Evan Cheng2008-06-301-4/+2
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-5/+5
* Dwarf requires variable entries to be in the source order. Right now, since w...Evan Cheng2008-02-041-1/+0
* explicitly include Compiler.h instead of getting it from tblgen in the middle...Chris Lattner2008-02-031-0/+1
* don't do ReplaceUses on a result that doesn't exist.Chris Lattner2008-02-031-2/+4
* SDIsel processes llvm.dbg.declare by recording the variable debug information...Evan Cheng2008-02-021-0/+1
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-1/+0
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} toDan Gohman2007-10-081-2/+2
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have the...Evan Cheng2007-07-101-12/+14
* Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.Evan Cheng2007-07-051-23/+171
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-13/+27
* match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.llChris Lattner2007-05-031-0/+1
* Fix naming inconsistencies.Evan Cheng2007-03-191-1/+1
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-191-2/+2
* AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]Evan Cheng2007-03-131-0/+23
* Get rid of references to iostream.Evan Cheng2007-02-071-1/+0
* Select add FI, c correctly.Evan Cheng2007-02-061-1/+6
* - Store val, [sp, c] must be selected to tSTRsp.Evan Cheng2007-02-061-4/+34
* Change the operand orders to t_addrmode_s* to make it easier to morphEvan Cheng2007-01-301-15/+15
* Use PC relative ldr to load from a constantpool in Thumb mode.Evan Cheng2007-01-241-8/+17
* Allow [ fi#c, imm ] as ARM load / store addresses.Evan Cheng2007-01-241-25/+39
* Various Thumb mode load / store isel bug fixes.Evan Cheng2007-01-241-13/+38
* - Reorg Thumb load / store instructions. Combine each rr and ri pair ofEvan Cheng2007-01-231-21/+38
* ARM backend contribution from Apple.Evan Cheng2007-01-191-986/+450
* Build constants using instructions mov/orr or mvn/eor.Lauro Ramos Venancio2007-01-121-20/+74
* Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).Lauro Ramos Venancio2007-01-041-0/+5
* implement missing comparesRafael Espindola2006-12-311-37/+66
* For PR950:Reid Spencer2006-12-311-1/+1
* fix commentRafael Espindola2006-12-291-1/+1
* Implement SELECT_CC (f32/f64) for ARM.Lauro Ramos Venancio2006-12-281-1/+3
* avoid using a constant table when a constant can be used inlineRafael Espindola2006-12-141-24/+82
* more general matching of the MVN instructionRafael Espindola2006-12-121-26/+11
* don't use "ordinary" addressing mode 1 when mvn is appropriateRafael Espindola2006-12-121-0/+2
* use MVN to handle small negative constantsRafael Espindola2006-12-121-0/+21
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
* expand memmove and memcpyRafael Espindola2006-12-051-0/+2
* add support for the "r" asm constraintRafael Espindola2006-12-051-0/+27
* implement load effective address similar to the alpha backendRafael Espindola2006-11-091-34/+11
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