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* Remove unused variable.Duncan Sands2012-02-231-1/+0
| | | | llvm-svn: 151251
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-3/+115
| | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-2/+1
| | | | llvm-svn: 149961
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-101-1/+1
| | | | | | rdar://10663487 llvm-svn: 147876
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-211-3/+14
| | | | llvm-svn: 147069
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-141-6/+15
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-8/+19
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-1/+2
| | | | llvm-svn: 145450
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-291-1/+2
| | | | llvm-svn: 145442
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-9/+33
| | | | llvm-svn: 143369
* Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen2011-10-271-1/+1
| | | | | | | Previously, we were only setting the alignment bits on over-aligned loads and stores. llvm-svn: 143160
* ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach2011-10-271-0/+4
| | | | llvm-svn: 143158
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-8/+34
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Fix misc warnings. Patch by Joe Abbey.Eli Friedman2011-10-181-1/+0
| | | | llvm-svn: 142332
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-101-0/+66
| | | | llvm-svn: 141591
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-101-66/+0
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* Disable ABS optimization for Thumb1 target, we don't have necessary ↵Anton Korobeynikov2011-10-081-0/+3
| | | | | | instructions there. llvm-svn: 141481
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-071-0/+63
| | | | | | Patch by Ana Pazos! llvm-svn: 141365
* Always merge profitable shifts on A9, not just when they have a single use.Cameron Zwarich2011-10-051-6/+2
| | | | llvm-svn: 141248
* Remove a check from ARM shifted operand isel helper methods, which were blockingCameron Zwarich2011-10-051-10/+0
| | | | | | | | merging an lsl #2 that has multiple uses on A9. This shift is free, so there is no problem merging it in multiple places. Other unprofitable shifts will not be merged. llvm-svn: 141247
* Add braces around something that throws me for a loop.Cameron Zwarich2011-10-051-1/+2
| | | | llvm-svn: 141173
* There is no point in setting out-parameters for a ComplexPattern function whenCameron Zwarich2011-10-051-1/+0
| | | | | | it returns false, at least as far as I could tell by reading the code. llvm-svn: 141172
* Also match negative offsets for addrmode3 and addrmode5.Jakob Stoklund Olesen2011-09-231-2/+2
| | | | | | | | Math is hard, and isScaledConstantInRange() always returned false for negative constants. It was doing unsigned division of negative numbers before casting back to signed. llvm-svn: 140425
* Tidy up a few 80 column violations.Jim Grosbach2011-09-131-4/+4
| | | | llvm-svn: 139636
* When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ↵Owen Anderson2011-08-311-1/+8
| | | | | | | | need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. <rdar://problem/10046188> llvm-svn: 138885
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-311-7/+13
| | | | llvm-svn: 138868
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-311-0/+32
| | | | llvm-svn: 138845
* addrmode_imm12 and addrmode2_offset encode their immediate values ↵Owen Anderson2011-08-291-4/+28
| | | | | | differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. llvm-svn: 138758
* Fix ARM codegen breakage caused by r138653.Owen Anderson2011-08-261-6/+15
| | | | llvm-svn: 138657
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-4/+4
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-2/+3
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* ARM refactor indexed store instructions.Jim Grosbach2011-08-051-2/+5
| | | | | | | | | | Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-2/+4
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-13/+40
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Fix test failures caused by my so_reg refactoring.Owen Anderson2011-07-221-2/+2
| | | | llvm-svn: 135785
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-11/+9
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, ↵Owen Anderson2011-07-211-15/+52
| | | | | | allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. llvm-svn: 135693
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-10/+12
| | | | | | ARM MC code from target. llvm-svn: 135636
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-3/+3
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-161-12/+23
| | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. llvm-svn: 133178
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-281-0/+105
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. llvm-svn: 132248
* Zap a couple now-unused functions.Eli Friedman2011-04-291-10/+0
| | | | llvm-svn: 130557
* This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson2011-04-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. llvm-svn: 129775
* Do not lose mem_operands while lowering VLD / VST intrinsics.Evan Cheng2011-04-191-4/+29
| | | | llvm-svn: 129738
* Reduce code duplication.Owen Anderson2011-03-181-31/+13
| | | | llvm-svn: 127899
* Generate a VTBL instruction instead of a series of loads and stores when weBill Wendling2011-03-141-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better than this: _shuf: @ BB#0: @ %entry push {r4, r7, lr} add r7, sp, #4 sub sp, #12 mov r4, sp bic r4, r4, #7 mov sp, r4 mov r2, sp vmov d16, r0, r1 orr r0, r2, #6 orr r3, r2, #7 vst1.8 {d16[0]}, [r3] vst1.8 {d16[5]}, [r0] subs r4, r7, #4 orr r0, r2, #5 vst1.8 {d16[4]}, [r0] orr r0, r2, #4 vst1.8 {d16[4]}, [r0] orr r0, r2, #3 vst1.8 {d16[0]}, [r0] orr r0, r2, #2 vst1.8 {d16[2]}, [r0] orr r0, r2, #1 vst1.8 {d16[1]}, [r0] vst1.8 {d16[3]}, [r2] vldr.64 d16, [sp] vmov r0, r1, d16 mov sp, r4 pop {r4, r7, pc} The "illegal" testcase in vext.ll is no longer illegal. <rdar://problem/9078775> llvm-svn: 127630
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-1/+1
| | | | llvm-svn: 127509
* Remove unused conditional negate operations.Bob Wilson2011-03-051-28/+0
| | | | llvm-svn: 127090
* Add patterns to use post-increment addressing for Neon VST1-lane instructions.Bob Wilson2011-02-251-0/+15
| | | | llvm-svn: 126477
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