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* Clean up a comment (indentation was wrong).Bob Wilson2009-10-081-1/+2
| | | | llvm-svn: 83565
* Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83526
* Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83518
* Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+1
| | | | llvm-svn: 83513
* Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83508
* Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83506
* Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+1
| | | | llvm-svn: 83502
* Add codegen support for NEON vst4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-9/+61
| | | | llvm-svn: 83486
* Add codegen support for NEON vst3 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-9/+55
| | | | llvm-svn: 83484
* Add codegen support for NEON vst2 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-7/+31
| | | | llvm-svn: 83482
* Add codegen support for NEON vld4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-7/+50
| | | | llvm-svn: 83479
* Add codegen support for NEON vld3 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-7/+48
| | | | llvm-svn: 83471
* Rearrange code for selecting vld2 intrinsics. No functionality change.Bob Wilson2009-10-071-9/+14
| | | | | | This is just to be more consistent with the forthcoming code for vld3/4. llvm-svn: 83470
* Add codegen support for NEON vld2 operations on quad registers.Bob Wilson2009-10-061-1/+36
| | | | llvm-svn: 83422
* Pass the optimization level when constructing the ARM instruction selector.Bob Wilson2009-09-281-4/+6
| | | | | | | Otherwise, it is always set to "default", which prevents debug info from even being generated during isel. Radar 7250345. llvm-svn: 82988
* Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.Anton Korobeynikov2009-09-271-10/+12
| | | | | | This should be better than single load from constpool. llvm-svn: 82948
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-251-36/+36
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Add support for generating code for vst{234}lane intrinsics.Bob Wilson2009-09-011-0/+55
| | | | llvm-svn: 80707
* Generate code for vld{234}_lane intrinsics.Bob Wilson2009-09-011-0/+57
| | | | llvm-svn: 80656
* Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.Bob Wilson2009-08-261-111/+115
| | | | | | | | The instructions can be selected directly from the intrinsics. We will need to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but those are not yet implemented. llvm-svn: 80117
* Record variable debug info at ISel time directly.Devang Patel2009-08-221-41/+0
| | | | llvm-svn: 79742
* Fix some typos and use type-based isel for VZIP/VUZP/VTRNAnton Korobeynikov2009-08-211-21/+42
| | | | llvm-svn: 79625
* Add nodes & dummy matchers for some v{zip,uzp,trn} instructionsAnton Korobeynikov2009-08-211-0/+30
| | | | llvm-svn: 79622
* Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these asBob Wilson2009-08-211-57/+0
| | | | | | | vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. llvm-svn: 79579
* Indentation.Evan Cheng2009-08-141-1/+1
| | | | llvm-svn: 79022
* During legalization, change Neon vdup_lane operations from shuffles toBob Wilson2009-08-141-41/+0
| | | | | | | | target-specific VDUPLANE nodes. This allows the subreg handling for the quad-register version to be done easily with Pats in the .td file, instead of with custom code in ARMISelDAGToDAG.cpp. llvm-svn: 78993
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
| | | | llvm-svn: 78948
* Shrink Thumb2 movcc instructions.Evan Cheng2009-08-121-1/+1
| | | | llvm-svn: 78790
* Add missing chain operands for VLD* and VST* instructions.Bob Wilson2009-08-121-12/+18
| | | | | | Set "mayLoad" and "mayStore" on the load/store instructions. llvm-svn: 78761
* Shrinkify Thumb2 r = add sp, imm.Evan Cheng2009-08-111-1/+1
| | | | llvm-svn: 78745
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-200/+200
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-25/+25
| | | | llvm-svn: 78666
* Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form toEvan Cheng2009-08-111-38/+31
| | | | | | | | | | match base only address, i.e. [r] since Thumb2 requires a offset register field. For those, use [r + imm12] where the immediate is zero. Note the generated assembly code does not look any different after the patch. But the bug would have broken the JIT (if there is Thumb2 support) and it can break later passes which expect the address mode to be well-formed. llvm-svn: 78658
* Use vAny type to get rid of Neon intrinsics that differed only in whetherBob Wilson2009-08-111-6/+3
| | | | | | | | | | | the overloaded vector types allowed floating-point or integer vector elements. Most of these operations actually depend on the element type, so bitcasting was not an option. If you include the vpadd intrinsics that I updated earlier, this gets rid of 20 intrinsics. llvm-svn: 78646
* Fix a bug where DAGCombine was producing an illegal ConstantFPDan Gohman2009-08-101-18/+0
| | | | | | | node after legalize, and remove the workaround code from the ARM backend. llvm-svn: 78615
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-206/+206
| | | | | | own struct type. llvm-svn: 78610
* Handle the constantfp created during post-legalization dag combiner phase.Evan Cheng2009-08-101-0/+18
| | | | llvm-svn: 78594
* Use VLDM / VSTM to spill/reload 128-bit Neon registersAnton Korobeynikov2009-08-081-0/+8
| | | | llvm-svn: 78468
* Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,Bob Wilson2009-08-081-0/+33
| | | | | | so I generalized the class for VTRN in the .td file to handle all 3 of them. llvm-svn: 78460
* Implement Neon VTRN instructions. For now, anyway, these are selectedBob Wilson2009-08-081-0/+27
| | | | | | | | directly from the intrinsics produced by the frontend. If it is more convenient to have a custom DAG node for using these to implement shuffles, we can add that later. llvm-svn: 78459
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-19/+57
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
* Implement Neon VST[234] operations.Bob Wilson2009-08-061-6/+59
| | | | llvm-svn: 78330
* Neon does not actually have VLD{234}.64 instructions.Bob Wilson2009-08-061-3/+0
| | | | | | These operations will have to be synthesized from other instructions. llvm-svn: 78263
* Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.Bob Wilson2009-08-051-1/+57
| | | | | | | | | Get rid of yesterday's code to fix the register usage during isel. Select the new DAG nodes to machine instructions. The new pre-alloc pass to choose adjacent registers for these results is not done, so the results of this will generally not assemble yet. llvm-svn: 78136
* Lower CONCAT_VECTOR during legalization instead of matching it during isel.Bob Wilson2009-08-031-21/+0
| | | | | | Add a testcase. llvm-svn: 77992
* Split t2MOVCCs since some assemblers do not recognize mov shifted register ↵Evan Cheng2009-08-011-3/+16
| | | | | | alias with predicate. llvm-svn: 77764
* Remove redundant match for frame index from imm8 addrmode, it is handled by ↵David Goodwin2009-07-301-24/+14
| | | | | | the imm12 addrmode. llvm-svn: 77632
* Cleanup and include code selection for some frame index cases.David Goodwin2009-07-301-20/+49
| | | | llvm-svn: 77622
* Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a ↵Evan Cheng2009-07-261-1/+1
| | | | | | low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. llvm-svn: 77172
* Revert the ConstantInt constructors back to their 2.5 forms where possible, ↵Owen Anderson2009-07-241-2/+1
| | | | | | thanks to contexts-on-types. More to come. llvm-svn: 77011
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