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path: root/llvm/lib/Target/ARM/ARMFastISel.cpp
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* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-15/+15
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-6/+6
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Add ARM fast-isel support for materializing the address of a global in cases ↵Eli Friedman2011-06-031-3/+17
| | | | | | | | where the global uses an indirect symbol. rdar://9431157 llvm-svn: 132522
* Fix ARM fast isel to correctly flag memory operands to stores. This fixesCameron Zwarich2011-05-281-5/+7
| | | | | | -verify-machineinstrs failures on several tests. llvm-svn: 132268
* Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076Eli Friedman2011-05-271-0/+2
| | | | llvm-svn: 132194
* Rewrite fast-isel integer cast handling to handle more cases, and to be ↵Eli Friedman2011-05-251-1/+77
| | | | | | | | | | simpler and more consistent. The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts). rdar://9437928 . llvm-svn: 132099
* Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for ↵Eli Friedman2011-05-251-0/+4
| | | | | | i8 and i16 values. llvm-svn: 132073
* Kill some dead code.Jim Grosbach2011-05-161-3/+1
| | | | llvm-svn: 131431
* Apparently the check for direct calls is unnecessary.Eric Christopher2011-05-021-2/+2
| | | | llvm-svn: 130716
* Switch to ImmLeaf (which can be used by FastISel) for a few more common ↵Eli Friedman2011-04-291-0/+1
| | | | | | ARM/Thumb2 patterns. llvm-svn: 130552
* Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, butEric Christopher2011-04-291-0/+23
| | | | | | if it ever did it needs the def machinery. llvm-svn: 130549
* Some cleanup and optimize fallthrough more.Eric Christopher2011-04-291-8/+13
| | | | llvm-svn: 130546
* Re-committing r130454, which does not in fact break anything.Eli Friedman2011-04-291-19/+2
| | | | | | | Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. rdar://problem/9338332 . llvm-svn: 130539
* Add trunc->branch support, this won't help with clang's i8->i1 truncationsEric Christopher2011-04-291-1/+24
| | | | | | for bools, but is a start. llvm-svn: 130534
* Update comments and checks to match reality.Eric Christopher2011-04-291-9/+2
| | | | llvm-svn: 130464
* Whitespace.Eric Christopher2011-04-291-11/+11
| | | | llvm-svn: 130463
* Revert r130454; apparently this doesn't actually work.Eli Friedman2011-04-281-2/+19
| | | | llvm-svn: 130462
* Fix a rather obscure crash caused by ARM fast-isel generating code which ↵Eli Friedman2011-04-281-19/+2
| | | | | | | | redefines a register. rdar://problem/9338332 . llvm-svn: 130454
* Be more layout aware here and swap the successor and branch conditionEric Christopher2011-04-281-1/+8
| | | | | | if it means we get a fallthrough. llvm-svn: 130404
* Correct result when a branch condition is live across a blockStuart Hastings2011-04-161-4/+10
| | | | | | boundary. <rdar://problem/8933028> llvm-svn: 129634
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-111-0/+1
| | | | llvm-svn: 129271
* Just use BL all the time. It's safer that way.Eric Christopher2011-04-051-9/+1
| | | | | | Fixes rdar://9184526 llvm-svn: 128869
* Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich2011-03-301-0/+30
| | | | | | can be recognized. This fixes <rdar://problem/9183078>. llvm-svn: 128584
* Migrate the fix in r128041 to ARM's fastisel support as well.Eric Christopher2011-03-221-13/+18
| | | | | | Fixes rdar://9169640 llvm-svn: 128100
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-121-6/+25
| | | | | | | | | Go ahead and add them on when we might want to use them and let later passes remove them. Fixes rdar://9118569 llvm-svn: 127518
* Only use blx for external function calls on thumb, these could be fixedEric Christopher2011-02-221-12/+26
| | | | | | | | | up by the dynamic linker, but it's better to use the correct instruction to begin with. Fixes rdar://9011034 llvm-svn: 126176
* Use the incoming VT not the VT of where we're trying to store to determineEric Christopher2011-01-271-2/+2
| | | | | | | | if we can store a value. Also, the exclusion is or, not and. Fixes rdar://8920247. llvm-svn: 124357
* Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin2011-01-181-4/+0
| | | | llvm-svn: 123707
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-1/+1
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* fix some -Wself-assign warnings.Chris Lattner2011-01-051-3/+3
| | | | llvm-svn: 122893
* Arm and thumb call instructions are also in different orders.Eric Christopher2010-12-211-13/+24
| | | | | | Fixes rdar://8782223 llvm-svn: 122313
* Don't handle -arm-long-calls in fast isel for now.Eric Christopher2010-12-151-0/+8
| | | | llvm-svn: 121919
* Refactor load/store handling again. Simplify and make some room forEric Christopher2010-12-011-103/+60
| | | | | | reg+reg handling. llvm-svn: 120526
* Noticed this on inspection, fix and update some comments.Eric Christopher2010-11-301-3/+4
| | | | llvm-svn: 120447
* Update fastisel for the changes in r120272.Eric Christopher2010-11-291-3/+7
| | | | llvm-svn: 120324
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-1/+1
| | | | llvm-svn: 119990
* Rewrite address handling to use a structure with all the possible addressEric Christopher2010-11-201-11/+76
| | | | | | mode variables. Handle frame indexes in load/store and allocas again. llvm-svn: 119912
* STRH only needs the additional operand, not t2STRH. Also invert conditionalEric Christopher2010-11-201-9/+5
| | | | | | to match the one from the load emitter above. llvm-svn: 119911
* Don't need to save piecemeal now.Eric Christopher2010-11-191-4/+2
| | | | llvm-svn: 119862
* Update comment.Eric Christopher2010-11-191-3/+2
| | | | llvm-svn: 119861
* Update comment.Eric Christopher2010-11-191-1/+1
| | | | llvm-svn: 119859
* Refactor address mode handling into a single struct (ala x86), thisEric Christopher2010-11-191-50/+72
| | | | | | | | should give allow a wider range of addressing modes. No functional change. llvm-svn: 119856
* Remove hard tabs.Jim Grosbach2010-11-191-2/+2
| | | | llvm-svn: 119810
* Recommit this change and remove the failing part of the test - it didn'tEric Christopher2010-11-151-4/+5
| | | | | | | pass in the first place and was masked by earlier failures not warning and aborting the block. llvm-svn: 119184
* Temporarily revert this.Eric Christopher2010-11-121-5/+4
| | | | llvm-svn: 118946
* Make this happen for ARM like x86. Don't entirely bail out whenEric Christopher2010-11-121-4/+5
| | | | | | | an address is in a different block, get it into a register and go from there. llvm-svn: 118936
* Fix up a few more spots of addrmode2 (or not) changes that wereEric Christopher2010-11-121-6/+12
| | | | | | | | missed. Update some comments accordingly. Fixes rdar://8652289 llvm-svn: 118888
* Trailing whitespace.Jim Grosbach2010-11-091-6/+6
| | | | llvm-svn: 118606
* Make sure we have movw on the target before using it.Eric Christopher2010-11-061-1/+1
| | | | | | Fixes 8559. llvm-svn: 118333
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-041-1/+1
| | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. llvm-svn: 118245
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