summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Remove another Darwin assembler workaround.Evan Cheng2009-08-121-2/+0
| | | | llvm-svn: 78779
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-1/+2
| | | | llvm-svn: 78717
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78666
* Cosmetic changes.Evan Cheng2009-08-111-8/+8
| | | | llvm-svn: 78655
* Error out, rather than infinite looping, if constant island pass can't converge.Evan Cheng2009-08-071-4/+12
| | | | llvm-svn: 78377
* tBfar is bl, which clobbers LR.Evan Cheng2009-08-071-1/+2
| | | | llvm-svn: 78370
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-011-23/+41
| | | | llvm-svn: 77781
* - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offsetEvan Cheng2009-07-311-6/+6
| | | | | | | is scaled by two. - Teach GetInstSizeInBytes about TBB and TBH. llvm-svn: 77701
* tbb / tbh instructions only branch forward, not backwards.Evan Cheng2009-07-291-2/+4
| | | | llvm-svn: 77522
* Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte ↵Evan Cheng2009-07-291-38/+144
| | | | | | / halfword. llvm-svn: 77422
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* Disable my constant island pass optimization (to make use soimm more ↵Evan Cheng2009-07-241-4/+2
| | | | | | effectively). It caused infinite looping on lencod. llvm-svn: 76995
* Make sure thumb2 jumptable entries are aligned.Evan Cheng2009-07-241-4/+5
| | | | llvm-svn: 76986
* Fix up ARM constant island pass for Thumb2.Evan Cheng2009-07-231-125/+129
| | | | | | Also fixed up code to fully use the SoImm field for ADR on ARM mode. llvm-svn: 76890
* Fixing cp island pass. Step 1: Determine whether the constant pool offset can beEvan Cheng2009-07-211-18/+23
| | | | | | | negative on an individual bases rather than basing on whether it's in thumb mode. llvm-svn: 76698
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+2
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-0/+2
| | | | llvm-svn: 75067
* 80 col violation.Evan Cheng2009-07-071-2/+2
| | | | llvm-svn: 74888
* Add a new addressing mode for NEON load/store instructions.Bob Wilson2009-07-011-0/+1
| | | | llvm-svn: 74658
* Improve Thumb-2 jump table support.David Goodwin2009-06-301-1/+5
| | | | llvm-svn: 74549
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-6/+30
| | | | llvm-svn: 74543
* Implement Thumb2 ldr.Evan Cheng2009-06-291-4/+7
| | | | | | After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. llvm-svn: 74420
* Fix up a few minor typos in comments.Bob Wilson2009-05-121-7/+7
| | | | llvm-svn: 71563
* Fix 80-col violations and remove trailing whitespace. No functional changes.Bob Wilson2009-05-121-69/+71
| | | | llvm-svn: 71562
* Rename PaddedSize to AllocSize, in the hope that thisDuncan Sands2009-05-091-1/+1
| | | | | | | will make it more obvious what it represents, and stop it being confused with the StoreSize. llvm-svn: 71349
* Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen2009-02-131-8/+14
| | | | llvm-svn: 64429
* Suppress a compile time warning.Evan Cheng2009-01-281-0/+2
| | | | llvm-svn: 63161
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-121-1/+1
| | | | | | suggested by Chris. llvm-svn: 62099
* Use ARMFunctionInfo to track number of constpool entries and jumptables.Evan Cheng2008-11-081-5/+2
| | | | llvm-svn: 58877
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-3/+3
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-1/+1
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Tidy up several unbeseeming casts from pointer to intptr_t.Dan Gohman2008-09-041-1/+1
| | | | llvm-svn: 55779
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-8/+9
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-10/+10
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-1/+1
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-2/+2
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-11/+11
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-1/+1
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Eliminate the remaining uses of getTypeSize. ThisDuncan Sands2007-11-051-1/+1
| | | | | | | | | | | | | | should only effect x86 when using long double. Now 12/16 bytes are output for long double globals (the exact amount depends on the alignment). This brings globals in line with the rest of LLVM: the space reserved for an object is now always the ABI size. One tricky point is that only 10 bytes should be output for long double if it is a field in a packed struct, which is the reason for the additional argument to EmitGlobalConstant. llvm-svn: 43688
* ARM: make branch folder remove unconditional branchesDale Johannesen2007-07-121-5/+2
| | | | | | | | following jump tables that it earlier inserted. This would be OK on other targets but is needed for correctness only on ARM (constant islands needs to find jump tables). llvm-svn: 39782
* Fix hang compiling TimberWolf (allow for islandsDale Johannesen2007-07-111-6/+7
| | | | | | of size other than 4). llvm-svn: 39743
* Didn't mean the last commit. Revert.Evan Cheng2007-07-101-8/+6
| | | | llvm-svn: 38515
* Update.Evan Cheng2007-07-101-6/+8
| | | | llvm-svn: 38513
* Reflects the chanegs made to PredicateOperand.Evan Cheng2007-07-051-1/+3
| | | | llvm-svn: 37898
* Fix comment.Evan Cheng2007-05-161-1/+1
| | | | llvm-svn: 37098
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-6/+6
| | | | llvm-svn: 37066
* Drop 'const'Devang Patel2007-05-031-2/+2
| | | | llvm-svn: 36662
OpenPOWER on IntegriCloud