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* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Fix a potential performance problem in placing ARM constant pools.Bob Wilson2009-10-151-29/+67
| | | | | | | | | | | | In the case where there are no good places to put constants and we fall back upon inserting unconditional branches to make new blocks, allow all constant pool references in range of those blocks to put constants there, even if that means resetting the "high water marks" for those references. This will still terminate because you can't keep splitting blocks forever, and in the bad cases where we have to split blocks, it is important to avoid splitting more than necessary. llvm-svn: 84202
* Be smarter about reusing constant pool entries.Bob Wilson2009-10-151-4/+17
| | | | llvm-svn: 84173
* Fix another problem with ARM constant pools. Radar 7303551.Bob Wilson2009-10-151-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | When ARMConstantIslandPass cannot find any good locations (i.e., "water") to place constants, it falls back to inserting unconditional branches to make a place to put them. My recent change exposed a problem in this area. We may sometimes append to the same block more than one unconditional branch. The symptoms of this are that the generated assembly has a branch to an undefined label and running llc with -debug will cause a seg fault. This happens more easily since my change to prevent CPEs from moving from lower to higher addresses as the algorithm iterates, but it could have happened before. The end of the block may be in range for various constant pool references, but the insertion point for new CPEs is not right at the end of the block -- it is at the end of the CPEs that have already been placed at the end of the block. The insertion point could be out of range. When that happens, the fallback code will always append another unconditional branch if the end of the block is in range. The fix is to only append an unconditional branch if the block does not already end with one. I also removed a check to see if the constant pool load instruction is at the end of the block, since that is redundant with checking if the end of the block is in-range. There is more to be done here, but I think this fixes the immediate problem. llvm-svn: 84172
* Fix regression introduced by r83894.Bob Wilson2009-10-131-1/+2
| | | | llvm-svn: 83982
* Delete a comment that makes no sense to me. The statement that moving a CPEBob Wilson2009-10-121-2/+1
| | | | | | | | | before its reference is only supported on ARM has not been true for a while. In fact, until recently, that was only supported for Thumb. Besides that, CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have no effect on Thumb alignment. llvm-svn: 83916
* Change CreateNewWater method to return NewMBB by reference.Bob Wilson2009-10-121-8/+8
| | | | llvm-svn: 83905
* Last week, ARMConstantIslandPass was failing to converge for theBob Wilson2009-10-121-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MultiSource/Benchmarks/MiBench/automotive-susan test. The failure has since been masked by an unrelated change (just randomly), so I don't have a testcase for this now. Radar 7291928. The situation where this happened is that a constant pool entry (CPE) was placed at a lower address than the load that referenced it. There were in fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were close together in the code. The distance from the loads to the CPEs was right at the limit of what they could handle, so that only one of the CPEs could be placed within range. On every iteration, the first CPE was found to be out of range, causing a new CPE to be inserted. The second CPE had been in range but the newly inserted entry pushed it too far away. Thus the second CPE was also replaced by a new entry, which in turn pushed the first CPE out of range. Etc. Judging from some comments in the code, the initial implementation of this pass did not support CPEs placed _before_ their references. In the case where the CPE is placed at a higher address, the key to making the algorithm terminate is that new CPEs are only inserted at the end of a group of adjacent CPEs. This is implemented by removing a basic block from the "WaterList" once it has been used, and then adding the newly inserted CPE block to the list so that the next insertion will come after it. This avoids the ping-pong effect where CPEs are repeatedly moved to the beginning of a group of adjacent CPEs. This does not work when going backwards, however, because the entries at the end of an adjacent group of CPEs are closer than the CPEs earlier in the group. To make this pass terminate, we need to maintain a property that changes can only happen in some sort of monotonic fashion. The fix used here is to require that the CPE for a particular constant pool load can only move to lower addresses. This is a very simple change to the code and should not cause any significant degradation in the results. llvm-svn: 83902
* Another minor clean-up.Bob Wilson2009-10-121-5/+5
| | | | llvm-svn: 83897
* Remove redundant parameter.Bob Wilson2009-10-121-8/+6
| | | | llvm-svn: 83894
* Use early exit to reduce indentation.Bob Wilson2009-10-121-19/+20
| | | | llvm-svn: 83874
* Change to return a value by reference.Bob Wilson2009-10-121-6/+6
| | | | llvm-svn: 83873
* Add a typedef for an iterator.Bob Wilson2009-10-121-6/+8
| | | | llvm-svn: 83872
* ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng2009-10-011-2/+4
| | | | llvm-svn: 83214
* eliminate the last DOUTs from the targets.Chris Lattner2009-08-231-12/+14
| | | | llvm-svn: 79833
* remove various std::ostream version of printing methods fromChris Lattner2009-08-231-13/+16
| | | | | | | | MachineInstr and MachineOperand. This required eliminating a bunch of stuff that was using DOUT, I hope that bill doesn't mind me stealing his fun. ;-) llvm-svn: 79813
* Also shrink immediate branches; also more assembler workarounds.Evan Cheng2009-08-141-7/+54
| | | | llvm-svn: 79014
* Shrink ADR and LDR from constantpool late during constantpool island pass.Evan Cheng2009-08-141-11/+72
| | | | llvm-svn: 78970
* tPOP_RET now has predicate operands.Evan Cheng2009-08-131-2/+2
| | | | llvm-svn: 78898
* Remove another Darwin assembler workaround.Evan Cheng2009-08-121-2/+0
| | | | llvm-svn: 78779
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-1/+2
| | | | llvm-svn: 78717
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78666
* Cosmetic changes.Evan Cheng2009-08-111-8/+8
| | | | llvm-svn: 78655
* Error out, rather than infinite looping, if constant island pass can't converge.Evan Cheng2009-08-071-4/+12
| | | | llvm-svn: 78377
* tBfar is bl, which clobbers LR.Evan Cheng2009-08-071-1/+2
| | | | llvm-svn: 78370
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-011-23/+41
| | | | llvm-svn: 77781
* - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offsetEvan Cheng2009-07-311-6/+6
| | | | | | | is scaled by two. - Teach GetInstSizeInBytes about TBB and TBH. llvm-svn: 77701
* tbb / tbh instructions only branch forward, not backwards.Evan Cheng2009-07-291-2/+4
| | | | llvm-svn: 77522
* Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte ↵Evan Cheng2009-07-291-38/+144
| | | | | | / halfword. llvm-svn: 77422
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* Disable my constant island pass optimization (to make use soimm more ↵Evan Cheng2009-07-241-4/+2
| | | | | | effectively). It caused infinite looping on lencod. llvm-svn: 76995
* Make sure thumb2 jumptable entries are aligned.Evan Cheng2009-07-241-4/+5
| | | | llvm-svn: 76986
* Fix up ARM constant island pass for Thumb2.Evan Cheng2009-07-231-125/+129
| | | | | | Also fixed up code to fully use the SoImm field for ADR on ARM mode. llvm-svn: 76890
* Fixing cp island pass. Step 1: Determine whether the constant pool offset can beEvan Cheng2009-07-211-18/+23
| | | | | | | negative on an individual bases rather than basing on whether it's in thumb mode. llvm-svn: 76698
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+2
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-0/+2
| | | | llvm-svn: 75067
* 80 col violation.Evan Cheng2009-07-071-2/+2
| | | | llvm-svn: 74888
* Add a new addressing mode for NEON load/store instructions.Bob Wilson2009-07-011-0/+1
| | | | llvm-svn: 74658
* Improve Thumb-2 jump table support.David Goodwin2009-06-301-1/+5
| | | | llvm-svn: 74549
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-6/+30
| | | | llvm-svn: 74543
* Implement Thumb2 ldr.Evan Cheng2009-06-291-4/+7
| | | | | | After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. llvm-svn: 74420
* Fix up a few minor typos in comments.Bob Wilson2009-05-121-7/+7
| | | | llvm-svn: 71563
* Fix 80-col violations and remove trailing whitespace. No functional changes.Bob Wilson2009-05-121-69/+71
| | | | llvm-svn: 71562
* Rename PaddedSize to AllocSize, in the hope that thisDuncan Sands2009-05-091-1/+1
| | | | | | | will make it more obvious what it represents, and stop it being confused with the StoreSize. llvm-svn: 71349
* Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen2009-02-131-8/+14
| | | | llvm-svn: 64429
* Suppress a compile time warning.Evan Cheng2009-01-281-0/+2
| | | | llvm-svn: 63161
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-121-1/+1
| | | | | | suggested by Chris. llvm-svn: 62099
* Use ARMFunctionInfo to track number of constpool entries and jumptables.Evan Cheng2008-11-081-5/+2
| | | | llvm-svn: 58877
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-3/+3
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
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