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* Darwin requires a frame pointer for all non-leaf functions to support correctJim Grosbach2009-11-211-1/+4
| | | | | | backtraces. llvm-svn: 89562
* Make the pass class name more explicit.Jim Grosbach2009-11-161-4/+6
| | | | llvm-svn: 88964
* make pass name a bit more clearJim Grosbach2009-11-161-1/+1
| | | | llvm-svn: 88961
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-2/+45
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* Add a bool flag to StackObjects telling whether they reference spillDavid Greene2009-11-121-2/+4
| | | | | | | | | | | | | slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
* Now that the default is 'enabled,' a separate command line option for ARM isJim Grosbach2009-11-091-8/+1
| | | | | | not necessary. llvm-svn: 86621
* Enable dynamic stack realignment by default.Jim Grosbach2009-11-091-1/+1
| | | | llvm-svn: 86604
* Set dynamic stack realignment to real values.Jim Grosbach2009-11-091-11/+3
| | | | llvm-svn: 86602
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-4/+4
| | | | llvm-svn: 86494
* Use aligned load/store instructions for spilling Q registers when we know ↵Jim Grosbach2009-11-081-2/+2
| | | | | | the stack slot is 128 bit aligned llvm-svn: 86425
* Grammar.Jim Grosbach2009-11-041-1/+1
| | | | llvm-svn: 86068
* Now that the memory leak from McCat/08-main has been fixed (86056), re-enableJim Grosbach2009-11-041-3/+9
| | | | | | | aggressive testing of dynamic stack alignment. Note that this is off by default, and enabled for LLCBETA nightly results. llvm-svn: 86064
* If a function has no stack frame at all, dynamic realignment isn't necessary.Jim Grosbach2009-11-041-0/+1
| | | | llvm-svn: 86057
* dynamic stack realignment necessitates scanning the floating point callee-Jim Grosbach2009-11-041-2/+2
| | | | | | saved instructions even if no stack adjustment for those saves is needed. llvm-svn: 86056
* Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.Evan Cheng2009-11-031-2/+9
| | | | llvm-svn: 85871
* Revert r85049, it is causing PR5367Anton Korobeynikov2009-11-031-0/+2
| | | | llvm-svn: 85847
* Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.Evan Cheng2009-11-011-6/+16
| | | | llvm-svn: 85743
* Dial back the realignment a bit.Jim Grosbach2009-10-301-9/+3
| | | | llvm-svn: 85546
* To get more thorough testing from llc-beta nightly runs, do dynamic stackJim Grosbach2009-10-291-4/+9
| | | | | | realignment regardless of whether it's strictly necessary. llvm-svn: 85476
* Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach2009-10-281-31/+4
| | | | | | Thumb2. llvm-svn: 85406
* Enable virtual register based frame index scavenging by default for ARM & T2.Jim Grosbach2009-10-271-2/+2
| | | | llvm-svn: 85335
* Infrastructure for dynamic stack realignment on ARM. For now, this is off byJim Grosbach2009-10-271-2/+74
| | | | | | | default behind a command line option. This will enable better performance for vectors on NEON enabled processors. llvm-svn: 85333
* Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.Evan Cheng2009-10-251-0/+27
| | | | llvm-svn: 85049
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+1
| | | | llvm-svn: 84798
* Conditionalize ARM/T2 frame index post-scavenging while working out fixesJim Grosbach2009-10-211-4/+31
| | | | | | for a few bugs. llvm-svn: 84791
* Disable by default while debuggingJim Grosbach2009-10-201-1/+1
| | | | llvm-svn: 84669
* add cmd line opt to disable frame index reuse for ARM and T2. debug aid.Jim Grosbach2009-10-201-0/+7
| | | | llvm-svn: 84664
* Enable post-pass frame index register scavenging for ARM and Thumb2Jim Grosbach2009-10-201-20/+8
| | | | llvm-svn: 84585
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-191-4/+2
| | | | llvm-svn: 84563
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-3/+5
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-3/+3
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* Clarify comment phrasing.Jim Grosbach2009-09-301-1/+1
| | | | llvm-svn: 83148
* When checking whether we need to reserve a register for the scavenger,Jim Grosbach2009-09-301-1/+7
| | | | | | the size of the saved frame pointer needs to be taken into account. llvm-svn: 83136
* minor cleanup and add clarifying commentJim Grosbach2009-09-291-7/+9
| | | | llvm-svn: 83117
* Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stackJim Grosbach2009-09-281-2/+4
| | | | | | slot for the register scavenger when compiling Thumb1 functions. llvm-svn: 83023
* Add some comments to clarify things that I discovered this week.Bob Wilson2009-09-251-2/+6
| | | | llvm-svn: 82773
* Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach2009-09-241-3/+5
| | | | | | | | | | | | | | | | | | | interest for this, as it currently reserves a register rather than using the scavenger for matierializing constants as needed. Instead of scavenging registers on the fly while eliminating frame indices, new virtual registers are created, and then a scavenged collectively in a post-pass over the function. This isolates the bits that need to interact with the scavenger, and sets the stage for more intelligent use, and reuse, of scavenged registers. For the time being, this is disabled by default. Once the bugs are worked out, the current scavenging calls in replaceFrameIndices() will be removed and the post-pass scavenging will be the default. Until then, -enable-frame-index-scavenging enables the new code. Currently, only the Thumb1 back end is set up to use it. llvm-svn: 82734
* Fix a typo in an assertion message.Bob Wilson2009-09-181-1/+1
| | | | llvm-svn: 82284
* Revert array initialization regclass change so that the initialization stays ↵Jim Grosbach2009-09-111-24/+20
| | | | | | static, not runtime. llvm-svn: 81560
* Update register class references to use the global constant ↵Jim Grosbach2009-09-111-25/+29
| | | | | | ARM::*RegisterClass names. llvm-svn: 81556
* Fix -Asserts warning, round two.Daniel Dunbar2009-08-281-3/+2
| | | | llvm-svn: 80354
* Fix -Asserts warning.Daniel Dunbar2009-08-281-2/+1
| | | | llvm-svn: 80338
* Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which ↵Evan Cheng2009-08-271-11/+21
| | | | | | cannot fold any immediate offset. llvm-svn: 80191
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-5/+1
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
* Do not use frame register to reference fixed stack objects if the function ↵Evan Cheng2009-08-151-12/+13
| | | | | | is frameless. llvm-svn: 79067
* Leaf functions which do not save CSRs can be frameless even with ↵Evan Cheng2009-08-141-1/+8
| | | | | | -disable-fp-elim. llvm-svn: 79039
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
| | | | llvm-svn: 78948
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-4/+4
| | | | llvm-svn: 78666
* Use tMOVgpr2gpr instead of t2MOVr.Evan Cheng2009-08-101-4/+7
| | | | llvm-svn: 78556
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-5/+6
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
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