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* In the presence of variable sized objects, allocate an emergency spill slot.Jim Grosbach2010-07-091-3/+10
| | | | | | rdar://8131327 llvm-svn: 108008
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-081-1/+2
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* When using ADDri to get the address of a stack object, 255 is a conservativeJakob Stoklund Olesen2010-06-181-0/+9
| | | | | | | limit on the offset that can be materialized without using the register scavenger. llvm-svn: 106312
* An attempt to fix the problem Anton reported withDale Johannesen2010-06-181-1/+2
| | | | | | | ARM tail calls. Don't know if it works, but it doesn't break Darwin. llvm-svn: 106309
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-3/+5
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* Early implementation of tail call for ARM.Dale Johannesen2010-06-031-0/+30
| | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-021-1/+1
| | | | | | and tidy up the comment describing it. llvm-svn: 105339
* Replace ARM's getCalleeSavedRegClasses with a simpler solutionRafael Espindola2010-06-021-91/+40
| | | | llvm-svn: 105335
* Use enums instead of literals in the ARM backend.Jakob Stoklund Olesen2010-05-251-16/+16
| | | | llvm-svn: 104573
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-241-51/+51
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with aJakob Stoklund Olesen2010-05-171-16/+17
| | | | | | | | | | | | | | | too large limit. The function would return immediately when finding an addrmode 3/5 instruction. It needs to keep scanning in case there is an addrmode 6 instruction which drops the limit to 0. A test case is very difficult to produce because it will only fail when the scavenger is used. rdar://problem/7894847 llvm-svn: 103995
* Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng2010-05-141-0/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. llvm-svn: 103835
* Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling2010-05-141-2/+2
| | | | | | | | | the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. llvm-svn: 103802
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-17/+50
| | | | llvm-svn: 103760
* Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.Bob Wilson2010-05-131-1/+3
| | | | | | Do not use those for Thumb1 functions. llvm-svn: 103730
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng2010-05-061-6/+35
| | | | | | coalescer bug that's fixed by 103170. llvm-svn: 103172
* Revert r103156 since it was breaking the build bots.Eric Christopher2010-05-061-35/+6
| | | | | | | | | | | Reverse-merging r103156 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMRegisterInfo.h U lib/Target/ARM/ARMBaseRegisterInfo.cpp U lib/Target/ARM/ARMBaseInstrInfo.cpp U lib/Target/ARM/ARMRegisterInfo.td llvm-svn: 103159
* Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q ↵Evan Cheng2010-05-061-6/+35
| | | | | | registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. llvm-svn: 103156
* Add ARM specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+7
| | | | llvm-svn: 102324
* Implement -disable-non-leaf-fp-elim which disable frame pointer eliminationEvan Cheng2010-04-211-2/+2
| | | | | | | optimization for non-leaf functions. This will be hooked up to gcc's -momit-leaf-frame-pointer option. rdar://7886181 llvm-svn: 101984
* ReuseFrameIndexVals is used in multiple files, so it can't be static.Dan Gohman2010-04-151-2/+5
| | | | llvm-svn: 101379
* Fix a bunch of namespace polution.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101376
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101334
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-2/+1
| | | | llvm-svn: 100214
* Fix a very bad typo. Since the register number was off by one, the ARMBob Wilson2010-03-201-1/+1
| | | | | | | | load/store optimizer would incorrectly think that registers D26 and D28 were consecutive and would generate a VLDM instruction to load them. The assembler was not convinced. llvm-svn: 99043
* Make sure the LR gets pushed in functions that use vaargs. This fixesJim Grosbach2010-03-101-0/+4
| | | | | | 400.perlbench for the nightly tests. llvm-svn: 98183
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-2/+5
| | | | | | | | | | is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. llvm-svn: 98086
* scavenged frame index value re-use gets confused when more than one baseJim Grosbach2010-03-091-1/+1
| | | | | | | | register is involved for thumb1. Work around this for the moment by only re-using SP-relative offsets. This is temporary 'til the code can distinguish multiple base registers. llvm-svn: 98071
* pr6478: The frame pointer spill frame index is only defined when there is aBob Wilson2010-03-041-1/+3
| | | | | | frame pointer. llvm-svn: 97755
* Create a stack frame on ARM whenJakob Stoklund Olesen2010-02-241-41/+41
| | | | | | | | | | | - Function uses all scratch registers AND - Function does not use any callee saved registers AND - Stack size is too big to address with immediate offsets. In this case a register must be scavenged to calculate the address of a stack object, and the scavenger needs a spare register or emergency spill slot. llvm-svn: 97071
* Remove an unused variable. Was this intentional?Chandler Carruth2010-02-241-1/+0
| | | | llvm-svn: 97022
* handle very large call frames when require SPAdj != 0 for Thumb1Jim Grosbach2010-02-241-1/+1
| | | | llvm-svn: 97013
* Spelling. s/suppor /support /Jim Grosbach2010-02-231-3/+3
| | | | llvm-svn: 96954
* Updated version of r96634 (which was reverted due to failing 176.gcc andJim Grosbach2010-02-221-0/+10
| | | | | | | | 126.gcc nightly tests. These failures uncovered latent bugs that machine DCE could remove one half of a stack adjust down/up pair, causing PEI to assert. This update fixes that, and the tests now pass. llvm-svn: 96822
* Clean up a bit and fix for when SPAdj != 0Jim Grosbach2010-02-221-3/+2
| | | | llvm-svn: 96818
* The predicate index isn't fixed, so scan for it to make sure we get the properJim Grosbach2010-02-221-2/+3
| | | | | | | | | value. Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so remove the FIXME entry. llvm-svn: 96817
* Revert 96634. It causes assertion failures for 126.gcc and 176.gcc inBob Wilson2010-02-191-12/+3
| | | | | | the armv6 nightly tests. llvm-svn: 96691
* Radar 7636153. In the presence of large call frames, it's not sufficientJim Grosbach2010-02-191-3/+12
| | | | | | | | | for ARM to just check if a function has a FP to determine if it's safe to simplify the stack adjustment pseudo ops prior to eliminating frame indices. Allow targets to override the default behavior and does so for ARM and Thumb2. llvm-svn: 96634
* Teach MachineFrameInfo to track maximum alignment while stack objects are beingEvan Cheng2010-02-131-8/+0
| | | | | | | | | | created. This ensures it's updated at all time. It means targets which perform dynamic stack alignment would know whether it is required and whether frame pointer register cannot be made available register allocation. This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test case. llvm-svn: 96069
* As of r79039, we still try to eliminate the frame pointer on leaf functions,Jim Grosbach2010-02-021-1/+1
| | | | | | even when -disable-fp-elim is specified. llvm-svn: 95161
* constify a method argument.Chris Lattner2010-01-261-3/+4
| | | | llvm-svn: 94612
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-0/+8
| | | | | | | | | | | function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. llvm-svn: 93885
* 80 column violationsJim Grosbach2010-01-061-4/+6
| | | | llvm-svn: 92876
* Addressing mode 6 (load/store) instructions can't encode an immediate offsetJim Grosbach2010-01-061-1/+4
| | | | | | for stack references. llvm-svn: 92871
* Use proper move instructions. Make the verifier happy.Jakob Stoklund Olesen2009-12-221-1/+1
| | | | llvm-svn: 91914
* Dynamic stack realignment use of sp register as source/dest registerAnton Korobeynikov2009-12-061-4/+27
| | | | | | | | | | in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 llvm-svn: 90724
* Factor the stack alignment calculations out into a target independent pass.Jim Grosbach2009-12-021-63/+2
| | | | | | No functionality change. llvm-svn: 90336
* Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info ↵Jim Grosbach2009-11-221-1/+2
| | | | | | can get bogus values. llvm-svn: 89618
* Generate more correct debug info for frame indices.Jim Grosbach2009-11-221-35/+50
| | | | llvm-svn: 89576
* Revert 89562. We're being sneakier than I was giving us credit for, and thisJim Grosbach2009-11-211-4/+1
| | | | | | isn't necessary. llvm-svn: 89568
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