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* Enable virtual register based frame index scavenging by default for ARM & T2.Jim Grosbach2009-10-271-2/+2
| | | | llvm-svn: 85335
* Infrastructure for dynamic stack realignment on ARM. For now, this is off byJim Grosbach2009-10-271-2/+74
| | | | | | | default behind a command line option. This will enable better performance for vectors on NEON enabled processors. llvm-svn: 85333
* Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.Evan Cheng2009-10-251-0/+27
| | | | llvm-svn: 85049
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+1
| | | | llvm-svn: 84798
* Conditionalize ARM/T2 frame index post-scavenging while working out fixesJim Grosbach2009-10-211-4/+31
| | | | | | for a few bugs. llvm-svn: 84791
* Disable by default while debuggingJim Grosbach2009-10-201-1/+1
| | | | llvm-svn: 84669
* add cmd line opt to disable frame index reuse for ARM and T2. debug aid.Jim Grosbach2009-10-201-0/+7
| | | | llvm-svn: 84664
* Enable post-pass frame index register scavenging for ARM and Thumb2Jim Grosbach2009-10-201-20/+8
| | | | llvm-svn: 84585
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-191-4/+2
| | | | llvm-svn: 84563
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-3/+5
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-3/+3
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* Clarify comment phrasing.Jim Grosbach2009-09-301-1/+1
| | | | llvm-svn: 83148
* When checking whether we need to reserve a register for the scavenger,Jim Grosbach2009-09-301-1/+7
| | | | | | the size of the saved frame pointer needs to be taken into account. llvm-svn: 83136
* minor cleanup and add clarifying commentJim Grosbach2009-09-291-7/+9
| | | | llvm-svn: 83117
* Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stackJim Grosbach2009-09-281-2/+4
| | | | | | slot for the register scavenger when compiling Thumb1 functions. llvm-svn: 83023
* Add some comments to clarify things that I discovered this week.Bob Wilson2009-09-251-2/+6
| | | | llvm-svn: 82773
* Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach2009-09-241-3/+5
| | | | | | | | | | | | | | | | | | | interest for this, as it currently reserves a register rather than using the scavenger for matierializing constants as needed. Instead of scavenging registers on the fly while eliminating frame indices, new virtual registers are created, and then a scavenged collectively in a post-pass over the function. This isolates the bits that need to interact with the scavenger, and sets the stage for more intelligent use, and reuse, of scavenged registers. For the time being, this is disabled by default. Once the bugs are worked out, the current scavenging calls in replaceFrameIndices() will be removed and the post-pass scavenging will be the default. Until then, -enable-frame-index-scavenging enables the new code. Currently, only the Thumb1 back end is set up to use it. llvm-svn: 82734
* Fix a typo in an assertion message.Bob Wilson2009-09-181-1/+1
| | | | llvm-svn: 82284
* Revert array initialization regclass change so that the initialization stays ↵Jim Grosbach2009-09-111-24/+20
| | | | | | static, not runtime. llvm-svn: 81560
* Update register class references to use the global constant ↵Jim Grosbach2009-09-111-25/+29
| | | | | | ARM::*RegisterClass names. llvm-svn: 81556
* Fix -Asserts warning, round two.Daniel Dunbar2009-08-281-3/+2
| | | | llvm-svn: 80354
* Fix -Asserts warning.Daniel Dunbar2009-08-281-2/+1
| | | | llvm-svn: 80338
* Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which ↵Evan Cheng2009-08-271-11/+21
| | | | | | cannot fold any immediate offset. llvm-svn: 80191
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-5/+1
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
* Do not use frame register to reference fixed stack objects if the function ↵Evan Cheng2009-08-151-12/+13
| | | | | | is frameless. llvm-svn: 79067
* Leaf functions which do not save CSRs can be frameless even with ↵Evan Cheng2009-08-141-1/+8
| | | | | | -disable-fp-elim. llvm-svn: 79039
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
| | | | llvm-svn: 78948
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-4/+4
| | | | llvm-svn: 78666
* Use tMOVgpr2gpr instead of t2MOVr.Evan Cheng2009-08-101-4/+7
| | | | llvm-svn: 78556
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-5/+6
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-301-3/+8
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. llvm-svn: 77642
* Give getPointerRegClass() a "kind" value so that targets can Chris Lattner2009-07-291-4/+5
| | | | | | support multiple different pointer register classes. llvm-svn: 77501
* more simplifications and cleanup. :)Chris Lattner2009-07-281-18/+17
| | | | llvm-svn: 77350
* Code clean up. No functionality changes.Evan Cheng2009-07-281-21/+32
| | | | llvm-svn: 77301
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-203/+68
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* Get rid of more dead code.Evan Cheng2009-07-271-1/+1
| | | | llvm-svn: 77227
* Cosmetic change.Evan Cheng2009-07-271-2/+4
| | | | llvm-svn: 77222
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-1/+1
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate ↵Evan Cheng2009-07-271-10/+6
| | | | | | more getOpcode calls. llvm-svn: 77181
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-5/+7
| | | | llvm-svn: 77164
* 80 col violation.Evan Cheng2009-07-251-1/+2
| | | | llvm-svn: 77041
* Revert the ConstantInt constructors back to their 2.5 forms where possible, ↵Owen Anderson2009-07-241-2/+1
| | | | | | thanks to contexts-on-types. More to come. llvm-svn: 77011
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same ↵Evan Cheng2009-07-241-3/+3
| | | | | | instructions on all sub-targets. llvm-svn: 76925
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-118/+84
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-17/+54
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* 80 col violation.Evan Cheng2009-07-231-2/+4
| | | | llvm-svn: 76872
* Get rid one of the getRegisterNumbering. Also add D16 - D31.Evan Cheng2009-07-221-60/+71
| | | | llvm-svn: 76725
* Get rid of the Pass+Context magic.Owen Anderson2009-07-221-1/+1
| | | | llvm-svn: 76702
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-2/+3
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Move EVER MORE stuff over to LLVMContext.Owen Anderson2009-07-141-1/+4
| | | | llvm-svn: 75703
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