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* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-1/+1
| | | | | | single attribute in the future. llvm-svn: 170502
* Trim unneeded header #include.Jim Grosbach2012-12-111-1/+0
| | | | llvm-svn: 169933
* ARM: Remove old testing option.Jim Grosbach2012-12-111-5/+1
| | | | | | | Pre-regalloc frame allocation and referencing has been on by default for ages. No need for the testing option that disables it. llvm-svn: 169931
* ARM: Remove old testing options.Jim Grosbach2012-12-111-13/+0
| | | | | | Base pointer referencing has been enabled for ages. llvm-svn: 169930
* Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen2012-12-041-258/+0
| | | | | | | These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. llvm-svn: 169192
* Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen2012-12-031-0/+59
| | | | | | | This provides the same functionality as getRawAllocationOrder() for the even/odd hints, but without the many constant register arrays. llvm-svn: 169169
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-7/+7
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering allChad Rosier2012-11-061-0/+5
| | | | | | | | | | | | registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 llvm-svn: 167499
* Remove ARMBaseRegisterInfo::isReservedReg().Jakob Stoklund Olesen2012-10-261-37/+8
| | | | | | It is just as easy to use MRI::isReserved() now. llvm-svn: 166817
* Add GPRPair Register class to ARM.Jakob Stoklund Olesen2012-10-261-0/+12
| | | | | | | | | Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! llvm-svn: 166816
* Remove the canCombineSubRegIndices() target hook.Jakob Stoklund Olesen2012-10-261-116/+0
| | | | | | | The new coalescer can already do all of this, so there is no need to duplicate the efforts. llvm-svn: 166813
* Create enums for the different attributes.Bill Wendling2012-10-091-2/+3
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-131-1/+1
| | | | llvm-svn: 163803
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-281-7/+3
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. llvm-svn: 162732
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-271-3/+7
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. llvm-svn: 162713
* Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher2012-08-031-0/+12
| | | | | | | | but somehow managed to be dropped later. Patch by Karel Gardas. llvm-svn: 161226
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-2/+4
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Implement a bastardized ABI.Evan Cheng2012-04-271-2/+4
| | | | llvm-svn: 155686
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-3/+3
| | | | | | since they are equivalent. llvm-svn: 155188
* Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper2012-03-251-1/+0
| | | | llvm-svn: 153421
* remove unused variableMatt Beaumont-Gay2012-03-201-1/+0
| | | | llvm-svn: 153116
* Require a base pointer for stack realignment when SP may vary dynamically.Bob Wilson2012-03-201-2/+3
| | | | | | | | | | | | | ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects but not for stack adjustments around calls. Use hasReservedCallFrame() to check for both. The hasBasePointer function was already correctly checking both conditions, so the effect of this was that a base pointer would be used without checking whether the base pointer register could be reserved. I don't have a small testcase for this. <rdar://problem/11075906> llvm-svn: 153110
* Remove some redundant checks.Bob Wilson2012-03-201-2/+1
| | | | | | | ARMFrameLowering::hasReservedCallFrame is already checking for variable sized objects, so there's no point in checking it twice. llvm-svn: 153109
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-1/+1
| | | | llvm-svn: 152978
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-061-0/+1
| | | | | | | | | The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. llvm-svn: 152076
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-13/+13
| | | | | | static data size. llvm-svn: 151998
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Enable ARM base pointer when calling functions with large arguments.Jakob Stoklund Olesen2012-02-281-1/+21
| | | | | | | | | | | | | | | | | | When an outgoing call takes more than 2k of arguments on the stack, we don't allocate that call frame in the prolog, but adjust the stack pointer immediately before the call instead. This causes problems with the emergency spill slot because PEI can't track stack pointer adjustments on the second pass, and if the outgoing arguments are too big, SP can't be used to reach the emergency spill slot at all. Work around these problems by ensuring there is a base or frame pointer that can be used to access the emergency spill slot. <rdar://problem/10917166> llvm-svn: 151604
* Remove extra semi-colons.Chad Rosier2012-02-221-1/+1
| | | | llvm-svn: 151169
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames2012-02-171-1/+0
| | | | | | bail on reserved registers. This *should* be safe as of r150786. llvm-svn: 150769
* Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames2012-02-161-0/+1
| | | | llvm-svn: 150655
* FPSCR shouldn't be reserved.Lang Hames2012-02-161-1/+0
| | | | llvm-svn: 150654
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-4/+0
| | | | llvm-svn: 148578
* Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen2012-01-171-19/+5
| | | | | | Move ARM callee-saved lists into ARMCallingConv.td. llvm-svn: 148357
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-051-1/+1
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen2012-01-051-2/+17
| | | | | | | | | | | | | | | | | Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. llvm-svn: 147578
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-031-1/+1
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-201-1/+1
| | | | | | | | | | | Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. llvm-svn: 146997
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-3/+3
| | | | llvm-svn: 146981
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-191-98/+0
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-2/+2
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier2011-10-201-2/+5
| | | | llvm-svn: 142557
* Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier2011-10-181-5/+2
| | | | | | rdar://10288916 llvm-svn: 142337
* Revert r141529. This is causing failures in the test-suite, like bigstack ↵Bill Wendling2011-10-111-11/+2
| | | | | | and ReedSolomon. Boo... llvm-svn: 141716
* When getting the number of bits necessary for addressing modeBill Wendling2011-10-101-2/+11
| | | | | | | | ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. llvm-svn: 141529
* Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier2011-10-011-2/+5
| | | | | | to appease nightly testers. Not quite there yet. llvm-svn: 140953
* Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact Chad Rosier2011-10-011-5/+2
| | | | | | | | useful if an optimization assumes the stack has been realigned. Credit to Eli for his assistance. rdar://10043857 llvm-svn: 140924
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