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* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-4/+14
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate ↵Evan Cheng2009-07-271-2/+1
| | | | | | more getOpcode calls. llvm-svn: 77181
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* Remove unused member functions.Eli Friedman2009-07-241-10/+0
| | | | llvm-svn: 76960
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same ↵Evan Cheng2009-07-241-9/+1
| | | | | | instructions on all sub-targets. llvm-svn: 76925
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-9/+4
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-0/+7
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* Fix a regression from 76124. Thumb1 instructions default to S bit being true.Evan Cheng2009-07-191-0/+5
| | | | llvm-svn: 76374
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-2/+13
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* Move isPredicated from .cpp to .hEvan Cheng2009-07-101-1/+4
| | | | llvm-svn: 75217
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-0/+1
| | | | llvm-svn: 75036
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be ↵David Goodwin2009-07-081-0/+298
shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
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