summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
Commit message (Collapse)AuthorAgeFilesLines
...
* prune #includes a little.Chris Lattner2010-07-201-2/+3
| | | | llvm-svn: 108929
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-6/+0
| | | | llvm-svn: 108567
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-13/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-111-6/+4
| | | | llvm-svn: 108078
* Renumber NEON instruction formats to be consecutive.Bob Wilson2010-06-261-12/+12
| | | | llvm-svn: 106927
* Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm toBob Wilson2010-06-251-3/+3
| | | | | | "N..." instead of "NEON..." for consistency with the other NEON format names. llvm-svn: 106921
* Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.Bob Wilson2010-06-251-1/+3
| | | | | | Renumber MiscFrm to 25. llvm-svn: 106916
* Change if-conversion block size limit checks to add some flexibility.Evan Cheng2010-06-251-0/+11
| | | | llvm-svn: 106901
* We are missing opportunites to use ldm. Take code like this:Bill Wendling2010-06-231-0/+20
| | | | | | | | | | | | | | void t(int *cp0, int *cp1, int *dp, int fmd) { int c0, c1, d0, d1, d2, d3; c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); /* ... */ } It code gens into something pretty bad. But with this change (analogous to the X86 back-end), it will use ldm and generate few instructions. llvm-svn: 106693
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-0/+4
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-1/+2
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-1/+13
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-1/+1
| | | | llvm-svn: 105350
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-0/+5
| | | | llvm-svn: 104421
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-1/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* Frame index can be negative.Evan Cheng2010-04-291-1/+1
| | | | llvm-svn: 102577
* Add ARM specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+6
| | | | llvm-svn: 102324
* Renumber LdStExFrm from 28 to 11 and shift the existing format values to makeJohnny Chen2010-03-191-18/+18
| | | | | | | room for it. This is in preparation for another patch which is adding NEON subformats to facilitate disassembly. llvm-svn: 98967
* Attempt to appease the arm-linux buildbot by fixing the JIT encodings for newBob Wilson2010-03-131-2/+3
| | | | | | base register updating load/store-multiple instructions. llvm-svn: 98427
* Initial bits of ARMv4-only support.Anton Korobeynikov2010-03-061-1/+1
| | | | | | Patch by John Tytgat! llvm-svn: 97886
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-031-2/+2
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Add Target hook to duplicate machine instructions.Jakob Stoklund Olesen2010-01-061-0/+2
| | | | | | | Some instructions refer to unique labels, and so cannot be trivially cloned with CloneMachineInstr. llvm-svn: 92873
* Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in ↵Jim Grosbach2009-12-111-0/+2
| | | | | | progress. llvm-svn: 91090
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-3/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-301-2/+0
| | | | | | | | | for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. llvm-svn: 90144
* Refactor target hook for tail duplication as requested by Chris.Bob Wilson2009-11-241-2/+1
| | | | | | | | | | | | Make tail duplication of indirect branches much more aggressive (for targets that indicate that it is profitable), based on further experience with this transformation. I compiled 3 large applications with and without this more aggressive tail duplication and measured minimal changes in code size. ("size" on Darwin seems to round the text size up to the nearest page boundary, so I can only say that any code size increase was less than one 4k page.) Radar 7421267. llvm-svn: 89814
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-0/+16
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* Add predicate operand to NEON instructions. Fix lots (but not all) 80 col ↵Evan Cheng2009-11-211-0/+2
| | | | | | violations in ARMInstrNEON.td. llvm-svn: 89542
* Add a target hook to allow changing the tail duplication limit based on theBob Wilson2009-11-181-0/+3
| | | | | | | | | contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. llvm-svn: 89187
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-1/+2
| | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
* Refactor code.Evan Cheng2009-11-081-0/+5
| | | | llvm-svn: 86423
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-1/+1
| | | | llvm-svn: 86408
* Refactor code. Fix a potential missing check. Teach isIdentical() about ↵Evan Cheng2009-11-071-0/+3
| | | | | | tLDRpci_pic. llvm-svn: 86330
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-2/+1
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" ↵Anton Korobeynikov2009-11-021-1/+11
| | | | | | stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) llvm-svn: 85764
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-0/+5
| | | | | | | opcode and operand with a tab. Check for these instructions in the usual places. llvm-svn: 85411
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-1/+1
| | | | | | | | | instruction. This makes it re-materializable. Thumb2 will split it back out into two instructions so IT pass will generate the right mask. Also, this expose opportunies to optimize the movw to a 16-bit move. llvm-svn: 82982
* Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which ↵Evan Cheng2009-08-271-9/+10
| | | | | | cannot fold any immediate offset. llvm-svn: 80191
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-0/+5
| | | | llvm-svn: 79084
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-2/+2
| | | | llvm-svn: 78666
* Add support to reduce most of 32-bit Thumb2 arithmetic instructions.Evan Cheng2009-08-101-2/+3
| | | | llvm-svn: 78550
* Code refactoring. No functionality change.Evan Cheng2009-08-081-0/+5
| | | | llvm-svn: 78455
* A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR.Evan Cheng2009-08-071-1/+1
| | | | llvm-svn: 78418
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-2/+1
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-44/+59
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* More DCE.Evan Cheng2009-07-271-5/+1
| | | | llvm-svn: 77231
* Get rid of more dead code.Evan Cheng2009-07-271-2/+0
| | | | llvm-svn: 77227
* Clean up.Evan Cheng2009-07-271-0/+5
| | | | llvm-svn: 77221
OpenPOWER on IntegriCloud