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* Use BranchProbability instead of floating points in IfConverter.Jakub Staszak2011-07-101-4/+4
| | | | llvm-svn: 134858
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-1/+4
| | | | llvm-svn: 134244
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-6/+6
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Clean up a few 80 column violations.Jim Grosbach2011-06-131-2/+2
| | | | llvm-svn: 132946
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Fix a typo.Cameron Zwarich2011-04-131-3/+3
| | | | llvm-svn: 129429
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-311-22/+2
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-311-2/+22
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-311-22/+2
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-311-1/+19
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-301-19/+1
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-4/+4
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* VFP single precision arith instructions can go down to NEON pipeline, but on ↵Evan Cheng2011-02-221-1/+2
| | | | | | Cortex-A8 only. llvm-svn: 126238
* Sorry, several patches in one.Evan Cheng2011-01-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. llvm-svn: 123905
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-051-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
* s/ARM::BRIND/ARM::BX/g to coincide with r120366.Bill Wendling2010-11-301-1/+1
| | | | llvm-svn: 120371
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-271-19/+0
| | | | llvm-svn: 120228
* Rewrite stack callee saved spills and restores to use push/pop instructions.Eric Christopher2010-11-181-0/+15
| | | | | | | | | Remove movePastCSLoadStoreOps and associated code for simple pointer increments. Update routines that depended upon other opcodes for save/restore. Adjust all testcases accordingly. llvm-svn: 119725
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-0/+5
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* Code clean up. The peephole pass should be the one updating the instructionEvan Cheng2010-11-151-2/+1
| | | | | | iterator, not TII->OptimizeCompareInstr. llvm-svn: 119186
* Revert this temporarily.Eric Christopher2010-11-111-5/+0
| | | | llvm-svn: 118827
* Change the prologue and epilogue to use push/pop for the low ARM registers.Eric Christopher2010-11-111-0/+5
| | | | llvm-svn: 118823
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-7/+15
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+1
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-261-0/+2
| | | | llvm-svn: 117348
* Tidy up redundant check.Bob Wilson2010-10-261-1/+1
| | | | llvm-svn: 117331
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-0/+6
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-191-0/+5
| | | | | | | erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-191-5/+0
| | | | | | is", which breaks some nightly tests. llvm-svn: 116816
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-191-0/+5
| | | | | | | | | | | "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. llvm-svn: 116781
* Don't recompute MachineRegisterInfo in the Optimize* method.Bill Wendling2010-10-181-0/+1
| | | | llvm-svn: 116750
* MC machine encoding for simple aritmetic instructions that use a shiftedJim Grosbach2010-10-111-0/+5
| | | | | | register operand. llvm-svn: 116259
* Code refactoring.Evan Cheng2010-10-071-0/+16
| | | | llvm-svn: 116002
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-0/+15
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* Increase the number of bits used internally by the ARM target to represent theJim Grosbach2010-10-051-7/+7
| | | | | | addressing mode from four to five. llvm-svn: 115645
* Thread the determination of branch prediction hit rates back through the ↵Owen Anderson2010-10-011-3/+5
| | | | | | | | | if-conversion heuristic APIs. For now, stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide more nuanced estimates in the future. llvm-svn: 115364
* Part one of switching to using a more sane heuristic for determining ↵Owen Anderson2010-09-281-3/+5
| | | | | | | | | | | if-conversion profitability. Rather than having arbitrary cutoffs, actually try to cost model the conversion. For now, the constants are tuned to more or less match our existing behavior, but these will be changed to reflect realistic values as this work proceeds. llvm-svn: 114973
* Move the search for the appropriate AND instructionGabor Greif2010-09-211-2/+2
| | | | | | | | | | into OptimizeCompareInstr. This necessitates the passing of CmpValue around, so widen the virtual functions to accomodate. No functionality changes. llvm-svn: 114428
* handle the upper16/lower16 target operand flags on symbol references for MCJim Grosbach2010-09-171-16/+0
| | | | | | instruction lowering. llvm-svn: 114191
* Rename ConvertToSetZeroFlag to something more general.Bill Wendling2010-09-111-2/+2
| | | | llvm-svn: 113670
* No need to recompute the SrcReg and CmpValue.Bill Wendling2010-09-101-1/+2
| | | | llvm-svn: 113666
* Move some of the decision logic for converting an instruction into one that setsBill Wendling2010-09-101-2/+1
| | | | | | | the 'zero' bit down into the back-end. There are other cases where this logic isn't sufficient, so they should be handled separately. llvm-svn: 113665
* Modify the comparison optimizations in the peephole optimizer to update theBill Wendling2010-09-101-1/+2
| | | | | | | iterator when an optimization took place. This allows us to do more insane things with the code than just remove an instruction or two. llvm-svn: 113640
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-1/+1
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-091-0/+3
| | | | | | | | | | instruction in the class would be decoded to. Or zero if the number of uOPs must be determined dynamically. This will be used to determine the cost-effectiveness of predicating a micro-coded instruction. llvm-svn: 113513
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-28/+29
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Use the "isCompare" machine instruction attribute instead of calling theBill Wendling2010-08-081-6/+6
| | | | | | | | | relatively expensive comparison analyzer on each instruction. Also rename the comparison analyzer method to something more in line with what it actually does. This pass is will eventually be folded into the Machine CSE pass. llvm-svn: 110539
* Add the Optimize Compares pass (disabled by default).Bill Wendling2010-08-061-0/+11
| | | | | | | | | | | | | | | | This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. llvm-svn: 110423
* eliminate the TargetInstrInfo::GetInstSizeInBytes hook. Chris Lattner2010-07-221-1/+1
| | | | | | | | ARM/PPC/MSP430-specific code (which are the only targets that implement the hook) can directly reference their target-specific instrinfo classes. llvm-svn: 109171
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