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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Clean up.Evan Cheng2009-07-271-5/+1
| | | | llvm-svn: 77221
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-19/+31
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
* If CPSR is modified but the def is dead, then it's ok to fold the load / store.Evan Cheng2009-07-271-2/+3
| | | | llvm-svn: 77182
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate ↵Evan Cheng2009-07-271-13/+26
| | | | | | more getOpcode calls. llvm-svn: 77181
* Use the right instructions to copy between GPR and the more strictive tGPR ↵Evan Cheng2009-07-271-1/+1
| | | | | | classes. t2MOV does not match the RC requirements. llvm-svn: 77175
* Merge isLoadFromStackSlot into one since it behaves the same regardless of ↵Evan Cheng2009-07-271-12/+23
| | | | | | sub-target. llvm-svn: 77174
* Just use a single isMoveInstr to catch all the cases.Evan Cheng2009-07-271-6/+12
| | | | llvm-svn: 77173
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* Make sure thumb2 jumptable entries are aligned.Evan Cheng2009-07-241-8/+11
| | | | llvm-svn: 76986
* Remove unused member functions.Eli Friedman2009-07-241-56/+0
| | | | llvm-svn: 76960
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same ↵Evan Cheng2009-07-241-31/+25
| | | | | | instructions on all sub-targets. llvm-svn: 76925
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-8/+30
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-10/+0
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-2/+2
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* 80 col violation.Evan Cheng2009-07-111-2/+2
| | | | llvm-svn: 75358
* Move isPredicated from .cpp to .hEvan Cheng2009-07-101-5/+0
| | | | llvm-svn: 75217
* Change how so_imm and t2_so_imm are handled. At instruction selection time, ↵Evan Cheng2009-07-081-3/+2
| | | | | | the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. llvm-svn: 75048
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be ↵David Goodwin2009-07-081-0/+816
shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
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