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* Revert r181009.Amara Emerson2013-05-031-8/+8
| | | | llvm-svn: 181079
* Add support for reading ARM ELF build attributes.Amara Emerson2013-05-031-8/+8
| | | | | | | | | | | Build attribute sections can now be read if they exist via ELFObjectFile, and the llvm-readobj tool has been extended with an option to dump this information if requested. Regression tests are also included which exercise these features. Also update the docs with a fixed ARM ABI link and a new link to the Addenda which provides the build attributes specification. llvm-svn: 181009
* ARM: Fix an old refacto.Benjamin Kramer2013-03-151-1/+1
| | | | | | Fixes PR15520. llvm-svn: 177167
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-141-6/+9
| | | | | | | | inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi llvm-svn: 175186
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-131-9/+6
| | | | llvm-svn: 175107
* Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao2013-02-131-6/+9
| | | | | | on ARM llvm-svn: 175088
* Switch the code added in r173885 to use the new, shiny RTTIChandler Carruth2013-01-311-6/+2
| | | | | | | | | | | | | | | | | | | | | | | infrastructure on MCStreamer to test for whether there is an MCELFStreamer object available. This is just a cleanup on the AsmPrinter side of things, moving ad-hoc tests of random APIs to a direct type query. But the AsmParser completely broken. There were no tests, it just blindly cast its streamer to an MCELFStreamer and started manipulating it. I don't have a test case -- this actually failed on LLVM's own regression test suite. Unfortunately the failure only appears when the stars, compilers, and runtime align to misbehave when we read a pointer to a formatted_raw_ostream as-if it were an MCAssembler. =/ UBSan would catch this immediately. Many thanks to Matt for doing about 80% of the debugging work here in GDB, Jim for helping to explain how exactly to fix this, and others for putting up with the hair pulling that ensued during debugging it. llvm-svn: 174118
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-0/+7
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
* This patch implements runtime ARM specificJack Carter2013-01-301-0/+11
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173885
* Last in the series of removing unnecessary '0' arguments forEric Christopher2013-01-091-5/+5
| | | | | | | address space. Reordered the EmitULEB128IntValue arguments to make this easier. llvm-svn: 171949
* These functions have default arguments of 0 for the last arg. UseEric Christopher2013-01-091-2/+2
| | | | | | them. llvm-svn: 171933
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-4/+4
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-9/+9
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer2012-11-261-114/+78
| | | | llvm-svn: 168597
* Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer2012-11-261-376/+298
| | | | | | | | MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. llvm-svn: 168587
* Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko2012-11-151-1/+1
| | | | llvm-svn: 168049
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-101-25/+0
| | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 llvm-svn: 167657
* Recommit modified r167540.Amara Emerson2012-11-081-4/+19
| | | | | | | Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167574
* Revert r167540 until regression tests are updated.Amara Emerson2012-11-071-21/+4
| | | | llvm-svn: 167545
* Improve ARM build attribute emission for architectures types.Amara Emerson2012-11-071-4/+21
| | | | | | This also changes the default architecture emitted for a generic CPU to "v7". llvm-svn: 167540
* Remove some dead code from ARMAsmPrinter. Add virtual and LLVM_OVERRIDE to ↵Craig Topper2012-10-091-20/+0
| | | | | | the other methods. Mark some of the helper methods as private. llvm-svn: 165479
* Move TargetData to DataLayout.Micah Villmow2012-10-081-3/+3
| | | | llvm-svn: 165402
* ARM: locate user-defined text sections next to default text.Jim Grosbach2012-10-041-4/+20
| | | | | | | | | | | | Make sure functions located in user specified text sections (via the section attribute) are located together with the default text sections. Otherwise, for large object files, the relocations for call instructions are more likely to be out of range. This becomes even more likely in the presence of LTO. rdar://12402636 llvm-svn: 165254
* This needs braces. Spotted by Bill.Eric Christopher2012-08-141-1/+2
| | | | llvm-svn: 161906
* Add support for the %H output modifier.Eric Christopher2012-08-131-2/+15
| | | | | | Patch by Weiming Zhao. llvm-svn: 161768
* Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov2012-08-041-2/+8
| | | | llvm-svn: 161301
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-1/+1
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* Avoid depending on list orders and register numbering.Jakob Stoklund Olesen2012-05-301-6/+9
| | | | | | This code is covered by test/CodeGen/ARM/arm-modifier.ll. llvm-svn: 157720
* ARM: .end_data_region mismatch in Thumb2.Jim Grosbach2012-05-211-2/+5
| | | | | | | | | | 32-bit offset jump tables just use real branch instructions and so aren't marked as data regions. We were still emitting the .end_data_region marker though, which assert()ed. rdar://11499158 llvm-svn: 157221
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-21/+34
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 llvm-svn: 154480
* Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/11203543>Bob Wilson2012-04-071-2/+2
| | | | | | | | | | | | | | | | | The tLDRr instruction with the last register operand set to the zero register prints in assembly as if no register was specified, and the assembler encodes it as a tLDRi instruction with a zero immediate. With the integrated assembler, that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which is broken. Emit the instruction as tLDRi with a zero immediate. I don't know if there's a good way to write a testcase for this. Suggestions welcome. Opportunities for follow-up work: 1) The asm printer should complain if a non-optional register operand is set to the zero register, instead of silently dropping it. 2) The integrated assembler should complain in the same situation, instead of silently emitting the operand as "r0". llvm-svn: 154261
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+2
| | | | llvm-svn: 154226
* Deduplicate ARM call-related instructions.Jakob Stoklund Olesen2012-04-061-5/+0
| | | | | | | | We had special instructions for iOS because r9 is call-clobbered, but that is represented dynamically by the register mask operands now, so there is no need for the pseudo-instructions. llvm-svn: 154144
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-4/+0
| | | | llvm-svn: 153422
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-1/+1
| | | | llvm-svn: 152978
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-051-2/+2
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> llvm-svn: 152036
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-0/+54
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-54/+0
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-0/+54
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-211-3/+1
| | | | llvm-svn: 151083
* Strip the pointer casts from the constants here.Bill Wendling2012-02-151-1/+1
| | | | | | | | | The c'tor list is stored as a list of 'void ()*'s, so all of the functions are bitcast to that. However, the dyn_cast doesn't automagically look through bitcasts. Do that for it. <rdar://problem/10813350> llvm-svn: 150572
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-11/+9
| | | | llvm-svn: 149961
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-0/+16
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-3/+2
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. llvm-svn: 148759
* ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.NAKAMURA Takumi2012-01-231-2/+3
| | | | llvm-svn: 148694
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-3/+13
| | | | | | Patch by Ana Pazos! llvm-svn: 148658
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+1
| | | | llvm-svn: 148578
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+3
| | | | llvm-svn: 148473
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