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* Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov2012-08-041-2/+8
| | | | llvm-svn: 161301
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-1/+1
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* Avoid depending on list orders and register numbering.Jakob Stoklund Olesen2012-05-301-6/+9
| | | | | | This code is covered by test/CodeGen/ARM/arm-modifier.ll. llvm-svn: 157720
* ARM: .end_data_region mismatch in Thumb2.Jim Grosbach2012-05-211-2/+5
| | | | | | | | | | 32-bit offset jump tables just use real branch instructions and so aren't marked as data regions. We were still emitting the .end_data_region marker though, which assert()ed. rdar://11499158 llvm-svn: 157221
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-21/+34
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 llvm-svn: 154480
* Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/11203543>Bob Wilson2012-04-071-2/+2
| | | | | | | | | | | | | | | | | The tLDRr instruction with the last register operand set to the zero register prints in assembly as if no register was specified, and the assembler encodes it as a tLDRi instruction with a zero immediate. With the integrated assembler, that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which is broken. Emit the instruction as tLDRi with a zero immediate. I don't know if there's a good way to write a testcase for this. Suggestions welcome. Opportunities for follow-up work: 1) The asm printer should complain if a non-optional register operand is set to the zero register, instead of silently dropping it. 2) The integrated assembler should complain in the same situation, instead of silently emitting the operand as "r0". llvm-svn: 154261
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+2
| | | | llvm-svn: 154226
* Deduplicate ARM call-related instructions.Jakob Stoklund Olesen2012-04-061-5/+0
| | | | | | | | We had special instructions for iOS because r9 is call-clobbered, but that is represented dynamically by the register mask operands now, so there is no need for the pseudo-instructions. llvm-svn: 154144
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-4/+0
| | | | llvm-svn: 153422
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-1/+1
| | | | llvm-svn: 152978
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-051-2/+2
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> llvm-svn: 152036
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-0/+54
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-54/+0
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-0/+54
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-211-3/+1
| | | | llvm-svn: 151083
* Strip the pointer casts from the constants here.Bill Wendling2012-02-151-1/+1
| | | | | | | | | The c'tor list is stored as a list of 'void ()*'s, so all of the functions are bitcast to that. However, the dyn_cast doesn't automagically look through bitcasts. Do that for it. <rdar://problem/10813350> llvm-svn: 150572
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-11/+9
| | | | llvm-svn: 149961
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-0/+16
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-3/+2
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. llvm-svn: 148759
* ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.NAKAMURA Takumi2012-01-231-2/+3
| | | | llvm-svn: 148694
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-3/+13
| | | | | | Patch by Ana Pazos! llvm-svn: 148658
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+1
| | | | llvm-svn: 148578
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+3
| | | | llvm-svn: 148473
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-1/+0
| | | | llvm-svn: 147855
* Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>Bob Wilson2011-12-121-4/+14
| | | | | | | | | These modifiers simply select either the low or high D subregister of a Neon Q register. I've also removed the unimplemented 'p' modifier, which turns out to be a bit different than the comment here suggests and as far as I can tell was only intended for internal use in Apple's version of gcc. llvm-svn: 146417
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Align ARM constant pool islands via their basic block.Jakob Stoklund Olesen2011-12-061-2/+1
| | | | | | | | | | | Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. llvm-svn: 145890
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-4/+3
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-061-4/+3
| | | | llvm-svn: 143891
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-041-1/+20
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. llvm-svn: 141135
* Use the ARMConstantPoolMBB class to handle the MBB values.Bill Wendling2011-10-011-1/+1
| | | | llvm-svn: 140943
* Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling2011-10-011-1/+2
| | | | llvm-svn: 140939
* Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling2011-10-011-2/+4
| | | | | | and block addresses. llvm-svn: 140936
* Create a machine basic block in the constant pool and retrieve the symbol ↵Bill Wendling2011-09-291-0/+3
| | | | | | for an MBB. llvm-svn: 140824
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-0/+3
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-0/+4
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Tidy up. Formatting.Jim Grosbach2011-09-021-9/+10
| | | | llvm-svn: 139024
* Static relocation model Thumb jump table interworking.Jim Grosbach2011-08-311-0/+5
| | | | | | | Make sure the low bit of the PC is set when loading an address directly for jump tables in static relocation model. llvm-svn: 138912
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Move ARM frame-unwinding EHABI handling a touch earlier.Jim Grosbach2011-08-231-4/+4
| | | | | | | | It should go before AsmPrinter MC pseudo expansion since it's based on MachineInstr, not MCInst. Otherwise any frame related pseudo instructions may be missed. llvm-svn: 138386
* Add support for the R and Q constraints.Rafael Espindola2011-08-101-2/+22
| | | | llvm-svn: 137217
* Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin2011-08-091-11/+67
| | | | llvm-svn: 137115
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-1/+2
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-251-11/+0
| | | | llvm-svn: 135974
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-2/+2
| | | | | | ARM MC code from target. llvm-svn: 135636
* Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.Jim Grosbach2011-07-081-14/+0
| | | | llvm-svn: 134734
* Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.Jim Grosbach2011-07-081-12/+0
| | | | llvm-svn: 134732
* Use ARMPseudoExpand for ARM tail calls.Jim Grosbach2011-07-081-19/+1
| | | | llvm-svn: 134719
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