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* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-16/+4
| | | | | | | with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
* 98745 contains something unrelated to the patch.Johnny Chen2010-03-171-15/+1
| | | | | | Remove it from ARMAddressingModes.h. llvm-svn: 98751
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-171-1/+19
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
* Revert 98683. It is breaking something in the disassembler.Bob Wilson2010-03-161-4/+16
| | | | llvm-svn: 98692
* Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson2010-03-161-16/+4
| | | | | | | optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. llvm-svn: 98683
* Remove redundant writeback flag in ARM addressing mode 5.Bob Wilson2010-03-161-10/+6
| | | | llvm-svn: 98648
* Remove the writeback flag from ARM's address mode 4. Now that we have separateBob Wilson2010-03-161-9/+2
| | | | | | instructions for ld/st with writeback, the flag is completely redundant. llvm-svn: 98643
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-19/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-1/+19
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson2010-03-161-10/+0
| | | | | | | This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. llvm-svn: 98635
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-2/+2
| | | | llvm-svn: 86494
* Support alignment specifier for NEON vld/vst instructionsJim Grosbach2009-11-071-6/+8
| | | | llvm-svn: 86404
* Improve handling of immediates by splitting 32-bit immediates into two 16-bitJim Grosbach2009-10-211-0/+60
| | | | | | immediate operands when they will fit into the using instruction. llvm-svn: 84778
* reduce #includesChris Lattner2009-10-191-4/+3
| | | | llvm-svn: 84536
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-35/+35
| | | | llvm-svn: 78666
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-5/+6
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-3/+3
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-3/+4
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Change how so_imm and t2_so_imm are handled. At instruction selection time, ↵Evan Cheng2009-07-081-23/+0
| | | | | | the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. llvm-svn: 75048
* Add a new addressing mode for NEON load/store instructions.Bob Wilson2009-07-011-1/+23
| | | | llvm-svn: 74658
* Fix up a comment: besides the >80col lines, the operation for thisBob Wilson2009-07-011-6/+6
| | | | | | addressing mode is encoded in the second operand, not the third. llvm-svn: 74641
* Implement Thumb2 ldr.Evan Cheng2009-06-291-1/+1
| | | | | | After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. llvm-svn: 74420
* Initial Thumb2 support. Majority of the work is done by David Goodwin. There areEvan Cheng2009-06-231-0/+110
| | | | | | | | | | | | | also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng. I've done my best to consolidate the patches with those that were done by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed anything. I've completely reorganized the thumb2 td file, made more extensive uses of multiclass, etc. Test cases will be contributed later after I re-organize what's in svn first. llvm-svn: 73965
* Fix comment to match function name.Bob Wilson2009-03-301-1/+1
| | | | llvm-svn: 68050
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-1/+1
| | | | llvm-svn: 54128
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* ARM backend contribution from Apple.Evan Cheng2007-01-191-0/+394
llvm-svn: 33353
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