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* [ARM] Add PostRAScheduler optionSam Parker2017-08-181-4/+11
| | | | | | | | | | | This patch adds the option to allow also using the PostRA scheduler, which brings the ARM backend inline with AArch64 targets. The SchedModel can also set 'PostRAScheduler', as the R52 does, so also query this property in the overridden function. Differential Revision: https://reviews.llvm.org/D36866 llvm-svn: 311162
* [ARM] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer2017-08-111-0/+3
| | | | | | | | | Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
* [ARM][AArch64] ARMv8.3-A enablementSam Parker2017-08-101-0/+16
| | | | | | | | | | | | | | | | | The beta ARMv8.3 ISA specifications have been released for AArch64 and AArch32, these can be found at: https://developer.arm.com/products/architecture/a-profile/exploration-tools An introduction to this architecture update can be found at: https://community.arm.com/processors/b/blog/posts/armv8-a-architecture-2016-additions This patch is the first in a series which will add ARM v8.3-A support in LLVM and Clang. It adds the necessary changes that create targets for both the ARM and AArch64 backends. Differential Revision: https://reviews.llvm.org/D36514 llvm-svn: 310561
* [ARM] Remove FeatureNoARM implies ModeThumb.Florian Hahn2017-08-091-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: By removing FeatureNoARM implies ModeThumb, we can detect cases where a function's target-features contain -thumb-mode (enables ARM codegen for the function), but the architecture does not support ARM mode. Previously, the implication caused the FeatureNoARM bit to be cleared for functions with -thumb-mode, making the assertion in ARMSubtarget::ARMSubtarget [1] pointless for such functions. This assertion is the only guard against generating ARM code for architectures without ARM codegen support. Is there a place where we could easily generate error messages for the user? At the moment, we would generate ARM code for Thumb-only architectures. X86 has the same behavior as ARM, as in it only has an assertion and no error message, but I think for ARM an error message would be helpful. What do you think? For the example below, `llc -mtriple=armv7m-eabi test.ll -o -` will generate ARM assembler (or fail with an assertion error with this patch). Note that if we run the resulting assembler through llvm-mc, we get an appropriate error message, but not when codegen is handled through clang. ``` define void @bar() #0 { entry: ret void } attributes #0 = { "target-features"="-thumb-mode" } ``` [1] https://github.com/llvm-mirror/llvm/blob/c1f7b54cef62e9c8aa745d40bea146a167bf844e/lib/Target/ARM/ARMSubtarget.cpp#L147 Reviewers: t.p.northover, rengolin, peter.smith, aadg, silviu.baranga, richard.barton.arm, echristo Reviewed By: rengolin, echristo Subscribers: efriedma, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35569 llvm-svn: 310476
* [ARM] Add the option to directly access TLS pointerStrahinja Petrovic2017-07-281-0/+4
| | | | | | | | | This patch enables choice for accessing thread local storage pointer (like '-mtp' in gcc). Differential Revision: https://reviews.llvm.org/D34408 llvm-svn: 309381
* [ARM] Add use-misched feature, to enable the MachineScheduler.Florian Hahn2017-07-271-1/+6
| | | | | | | | | | | | | | | | | | | Summary: This change makes it easier to experiment with the MachineScheduler in the ARM backend and also makes it very explicit which CPUs use the MachineScheduler (currently only swift and cyclone). Reviewers: MatzeB, t.p.northover, javed.absar Reviewed By: MatzeB Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35935 llvm-svn: 309316
* [ARM] Minor cosmetic edits (NFC)Evandro Menezes2017-07-261-1/+1
| | | | | | Change the order of a case and the description for Exynos Mx processors. llvm-svn: 309184
* [ARM] Tidy up and organise better ARM.td. NFC.Javed Absar2017-07-131-183/+248
| | | | | | | | | | | This patch tidies up and organises ARM.td so that it is easier to understandand and extend in the future. Reviewed by: @hahn, @rovka Differential Revision: https://reviews.llvm.org/D35248 llvm-svn: 307897
* Rewrite ARM execute only support to avoid the use of a command line flag and ↵Eric Christopher2017-07-011-0/+4
| | | | | | | | unqualified ARMSubtarget lookup. Paired with a clang commit to use the new behavior. llvm-svn: 306927
* [ARM] Improve if-conversion for M-class CPUs without branch predictorsJohn Brawn2017-06-281-6/+20
| | | | | | | | | | | | | The current heuristic in isProfitableToIfCvt assumes we have a branch predictor, and so gives the wrong answer in some cases when we don't. This patch adds a subtarget feature to indicate that a subtarget has no branch predictor, and changes the heuristic in isProfitableToiIfCvt when it's present. This gives a slight overall improvement in a set of embedded benchmarks on Cortex-M4 and Cortex-M33. Differential Revision: https://reviews.llvm.org/D34398 llvm-svn: 306547
* [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).Kristof Beyls2017-06-281-1/+1
| | | | | | | | | | | | | | | | The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
* [ARM] Add macro fusion for AES instructions.Florian Hahn2017-06-221-1/+2
| | | | | | | | | | | | | | | | Summary: This patch adds a macro fusion using CodeGen/MacroFusion.cpp to pair AES instructions back to back and adds FeatureFuseAES to enable the feature. Reviewers: evandro, javed.absar, rengolin, t.p.northover Reviewed By: javed.absar Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34142 llvm-svn: 305988
* [ARM] Cortex-A57 scheduling model for ARM backend (AArch32)Javed Absar2017-06-021-6/+15
| | | | | | | | | | | | | | | This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
* ARM: add arm1176j-f processorTim Northover2017-05-021-0/+1
| | | | | | | | | I doubt anyone actually uses it, and I'm not even entirely convinced it exists myself; but it is our default for "clang -arch armv6". Functionally, if it does exist it's identical to the arm1176jz-f from LLVM's point of view (the difference is apparently in the "Security Extensions"). llvm-svn: 301962
* [ARM] Rename HW div feature to HW div Thumb. NFCI.Diana Picus2017-04-201-21/+22
| | | | | | | | | | | | | | | | The hardware div feature refers only to Thumb, but because of its name it is tempting to use it to check for hardware division in general, which may cause problems in ARM mode. See https://reviews.llvm.org/D32005. This patch adds "Thumb" to its name, to make its scope clear. One notable place where I haven't made the change is in the feature flag (used with -mattr), which is still hwdiv. Changing it would also require changes in a lot of tests, including clang tests, and it doesn't seem like it's worth the effort. Differential Revision: https://reviews.llvm.org/D32160 llvm-svn: 300827
* Revert "Revert "[ARM] Add Kryo to available targets""Yi Kong2017-04-061-1/+9
| | | | | | | | This reverts commit dc9458d5a747a02a9a8f198b84c2b92a6939a8dd. Added missing case for PreISelOperandLatencyAdjustment. llvm-svn: 299724
* Revert "[ARM] Add Kryo to available targets"Yi Kong2017-04-061-9/+1
| | | | | | | | This reverts commit 942d6e6f58bf7e63810dd7cbcbce1fdfa5ebc6d4. Build breakage. llvm-svn: 299689
* [ARM] Add Kryo to available targetsYi Kong2017-04-061-1/+9
| | | | | | | | | | | | | | | | Summary: Host CPU detection now supports Kryo, so we need to recognize it in ARM target. Reviewers: mcrosier, t.p.northover, rengolin, echristo, srhines Reviewed By: t.p.northover, echristo Subscribers: aemerson Differential Revision: https://reviews.llvm.org/D31775 llvm-svn: 299674
* [ARM] [Assembler] Support negative immediates for A32, T32 and T16Sanne Wouda2017-03-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
* [ARM] Replace HasT2ExtractPack with HasDSPSam Parker2017-02-171-16/+6
| | | | | | | | | | | Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
* [ARM] Add support for armv7ve triple in llvm (PR31358).George Burgess IV2017-02-091-10/+10
| | | | | | | | | | | | | | | Gcc supports target armv7ve which is armv7-a with virtualization extensions. This change adds support for this in llvm for gcc compatibility. Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as this is specified automatically by FeatureVirtualization. Patch by Manoj Gupta. Differential Revision: https://reviews.llvm.org/D29472 llvm-svn: 294661
* [globalisel][arm] Tablegen-erate current Register Bank Information.Daniel Sanders2017-02-051-0/+2
| | | | | | | | | | | | | | | | | | Summary: This patch tablegen-erates the ARM register bank information so that the static tables added in D27807 no longer need to be maintained. Depends on D27338 Reviewers: t.p.northover, rovka, ab, qcolombet, aditya_nandakumar Reviewed By: rovka Subscribers: aemerson, rengolin, mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D28567 llvm-svn: 294124
* [ARM] Enable Cortex-M23 and Cortex-M33 support.Javed Absar2017-02-011-0/+10
| | | | | | | | | | | | | Add both cores to the target parser and TableGen. Test that eabi attributes are set correctly for both cores. Additionally, test the absence and presence of MOVT in Cortex-M23 and Cortex-M33, respectively. Committed on behalf of Sanne Wouda. Reviewers : rengolin, olista01. Differential Revision: https://reviews.llvm.org/D29073 llvm-svn: 293761
* Add support for Samsung Exynos M3 (NFC)Evandro Menezes2016-12-131-0/+6
| | | | llvm-svn: 289613
* [ARM] Add machine scheduler for Cortex-R52 Javed Absar2016-11-151-1/+1
| | | | | | | | | | | | | This patch adds the Sched Machine Model for Cortex-R52. Details of the pipeline and descriptions are in comments in file ARMScheduleR52.td included in this patch. Reviewers: rengolin, jmolloy Differential Revision: https://reviews.llvm.org/D26500 llvm-svn: 286949
* [ARM] Assign cost of scaling for Cortex-R52Javed Absar2016-10-181-1/+2
| | | | | | | | | | | | This patch assigns cost of the scaling used in addressing for Cortex-R52. On Cortex-R52 a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode. Differential Revision: http://reviews.llvm.org/D25670 Reviewer: jmolloy llvm-svn: 284460
* [ARM]: Assign cost of scaling used in addressing mode for ARM coresJaved Absar2016-10-131-2/+6
| | | | | | | | | | | | | | | | | | | | | This patch assigns cost of the scaling used in addressing. On many ARM cores, a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode. For instance: LDR R0, [R1, R2 LSL #2] LDR R0, [R1, -R2 LSL #2] Above, (1) takes less cycles than (2). By assigning appropriate scaling factor cost, we enable the LLVM to make the right trade-offs in the optimization and code-selection phase. Differential Revision: http://reviews.llvm.org/D24857 Reviewers: jmolloy, rengolin llvm-svn: 284127
* [ARM]: Add Cortex-R52 target to LLVMJaved Absar2016-10-071-0/+17
| | | | | | | This patch adds Cortex-R52, the new ARM real-time processor, to LLVM. Cortex-R52 implements the ARMv8-R architecture. llvm-svn: 283542
* [AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes2016-08-011-0/+6
| | | | llvm-svn: 277364
* ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures.Tim Northover2016-07-191-32/+14
| | | | | | | | | | | There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". llvm-svn: 276013
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 1 flagDiana Picus2016-07-071-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes a command line flag that isn't used in any of the tests: check-vmlx-hazards. It can be replaced easily with the mattr mechanism, since this is now a subtarget feature. There is still some work left regarding FeatureExpandMLx. In the past MLx expansion was enabled for subtargets with hasVFP2(), until r129775 [1] switched from that to isCortexA9, without too much justification. In spite of that, the code performing MLx expansion still contains calls to isSwift/isLikeA9, although the results of those are pretty clear given that we're only enabling it for the A9. We should try to enable it for all targets that have FeatureHasVMLxHazards, as it seems to be closely related to that behaviour, and if that is possible try to clean up the MLx expansion pass from all calls to isWhatever. This will require some performance testing, so it will be done in another patch. [1] http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20110418/119725.html Differential Revision: http://reviews.llvm.org/D21798 llvm-svn: 274742
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-061-0/+5
| | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 llvm-svn: 274620
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCIDiana Picus2016-07-061-0/+19
| | | | | | | | | | | This is a follow-up for r273544 and r273853. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also marks them as obsolete. Differential Revision: http://reviews.llvm.org/D21796 llvm-svn: 274616
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 2). NFCIDiana Picus2016-06-271-0/+15
| | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21685 llvm-svn: 273853
* [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCIDiana Picus2016-06-231-7/+45
| | | | | | | | | | | | | This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-031-17/+22
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* This adds support for Cortex-A73 as an available target.Sjoerd Meijer2016-06-021-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D20865 llvm-svn: 271508
* Replace a string comparison in ARMSubtarget.h with a tablegen entry in ↵Artyom Skrobov2016-03-231-2/+4
| | | | | | | | | | | | ARM.td (NFC) Reviewers: rengolin, t.p.northover Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D18393 llvm-svn: 264165
* [ARM] Add Cortex-A32 supportRenato Golin2016-03-211-0/+8
| | | | | | | | Adding Cortex-A32 as an available target in the ARM backend. Patch by Sam Parker. llvm-svn: 263956
* [ARM] Cortex-R8 supportAlexandros Lamprineas2016-03-101-0/+12
| | | | | | | | | | | This patch adds Cortex-R8 to Target Parser and TableGen. It also adds CodeGen tests for the build attributes. Patch by Pablo Barrio. Differential Revision: http://reviews.llvm.org/D17925 llvm-svn: 263132
* Removed FeatureVFPOnlySP from the Cortex-R7 processor modelSjoerd Meijer2016-02-021-1/+0
| | | | | | | | | description and changed the regression test accordingly. The default configuration of a Cortex-R7 is to implement the VFPv3-D16 architecture and the feature line as it was is too restrictive. llvm-svn: 259480
* [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-251-0/+4
| | | | | | | | This patch was originally committed as r257883, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258681
* Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M ↵Reid Kleckner2016-01-151-4/+0
| | | | | | | | | | Baseline/Mainline" This reverts commit r257883. Somehow this didn't make it into r257916. llvm-svn: 257919
* [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-151-0/+4
| | | | llvm-svn: 257883
* [ARM] Add ARMv8-A semaphore/atomic instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-151-1/+1
| | | | llvm-svn: 257882
* [ARM] Add ARMv8-M Baseline/Mainline LLVM targetingBradley Smith2016-01-151-1/+24
| | | | llvm-svn: 257878
* [ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate ↵Bradley Smith2016-01-151-3/+9
| | | | | | features llvm-svn: 257877
* [AArch64] Add support for Samsung Exynos-M1MinSeong Kim2016-01-051-0/+8
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15663 llvm-svn: 256828
* [ARM] Flag vcvt{t,b} with an f16 type specifier as part of the FP16 extensionBradley Smith2015-12-071-0/+1
| | | | | | Additionally correct the Cortex-R7 definition to allow the FP16 feature. llvm-svn: 254900
* [AArch64]: Add support for Cortex-A35Christof Douma2015-12-021-0/+9
| | | | | | Adds support for the new Cortex-A35 ARMv8-A core. llvm-svn: 254503
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