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* Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng2010-08-111-2/+5
| | | | | | support it. e.g. cortex-m* processors. llvm-svn: 110798
* ArchV7M implies HW division instructions.Evan Cheng2010-08-111-3/+3
| | | | llvm-svn: 110797
* ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.Evan Cheng2010-08-111-11/+10
| | | | llvm-svn: 110796
* Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng2010-08-111-31/+35
| | | | llvm-svn: 110795
* Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng2010-08-111-0/+5
| | | | | | instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-111-4/+10
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable ↵Evan Cheng2010-08-091-0/+3
| | | | | | more 32-bit to 16-bit optimizations. llvm-svn: 110584
* Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).Evan Cheng2010-07-131-1/+3
| | | | llvm-svn: 108256
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-051-3/+8
| | | | | | | instructions to subtarget features and update tests to reflect. PR5717. llvm-svn: 103136
* Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch byJim Grosbach2010-05-051-0/+3
| | | | | | | | | Jordy <snhjordy@gmail.com>. Followup patches will add some tests and adjust to use Subtarget features for the instructions. llvm-svn: 103119
* Some bits of A9 scheduling: VFPAnton Korobeynikov2010-04-071-1/+2
| | | | llvm-svn: 100643
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-17/+1
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* vml[as] are slow on 1136jf-s also.Jim Grosbach2010-04-011-1/+2
| | | | llvm-svn: 100066
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-251-3/+10
| | | | | | Re-commit. This time complete with testsuite updates. llvm-svn: 99570
* need to fix 'make check' tests first. revert for a moment.Jim Grosbach2010-03-251-10/+3
| | | | llvm-svn: 99569
* switch the flag for using NEON for SP floating point to a subtarget 'feature'Jim Grosbach2010-03-251-3/+10
| | | | llvm-svn: 99568
* switch the use-vml[as] instructions flag to a subtarget 'feature'Jim Grosbach2010-03-251-1/+10
| | | | llvm-svn: 99565
* Add substarget feature for FP16Anton Korobeynikov2010-03-141-0/+2
| | | | llvm-svn: 98503
* Add ARMv6 itineraries.David Goodwin2009-11-181-8/+10
| | | | llvm-svn: 89218
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" ↵Anton Korobeynikov2009-11-021-2/+6
| | | | | | stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) llvm-svn: 85764
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-011-4/+1
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin2009-10-011-5/+1
| | | | | | specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. llvm-svn: 83215
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-301-1/+5
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-231-18/+9
| | | | llvm-svn: 82657
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ↵David Goodwin2009-08-111-1/+1
| | | | | | counter. llvm-svn: 78736
* Make NEON single-precision FP support the default for cortex-a8 (again).David Goodwin2009-08-071-1/+1
| | | | llvm-svn: 78430
* Disable NEON single-precision FP support for Cortex-A8, for now...David Goodwin2009-08-051-1/+1
| | | | llvm-svn: 78209
* By default, for cortex-a8 use NEON for single-precision FP. David Goodwin2009-08-051-4/+4
| | | | llvm-svn: 78200
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-041-0/+3
| | | | | | to enable. Added patterns for some binary FP operations. llvm-svn: 78081
* Add fake v7 itineraries for now.Evan Cheng2009-07-211-4/+6
| | | | llvm-svn: 76612
* Add a Thumb2 instruction flag to that indicates whether the instruction can ↵Evan Cheng2009-07-081-3/+3
| | | | | | be transformed to 16-bit variant. llvm-svn: 74988
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ↵Evan Cheng2009-06-191-42/+52
| | | | | | we are only using branch latency to determine if-conversion limits. llvm-svn: 73747
* Separate V6 from V6T2 since the latter has some extra nice instructionsAnton Korobeynikov2009-06-081-2/+6
| | | | llvm-svn: 73085
* Add placeholder for thumb2 stuffAnton Korobeynikov2009-05-291-5/+10
| | | | llvm-svn: 72593
* Add ARMv7 architecture, Cortex processors and different FPU modes handling.Anton Korobeynikov2009-05-231-1/+10
| | | | llvm-svn: 72337
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-171-0/+2
| | | | | | for ARM. Patch by Sandeep Patel. llvm-svn: 69371
* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-1/+1
| | | | | | they can be distributed along with the header files. llvm-svn: 59953
* Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 ↵Evan Cheng2008-11-061-3/+1
| | | | | | encoding bug. llvm-svn: 58800
* Restructure ARM code emitter to use instruction formats instead of ↵Evan Cheng2008-11-051-1/+3
| | | | | | addressing modes to determine how to encode instructions. llvm-svn: 58764
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-071-2/+4
| | | | llvm-svn: 40887
* Add a processor.Lauro Ramos Venancio2007-05-041-0/+1
| | | | llvm-svn: 36765
* ARM backend contribution from Apple.Evan Cheng2007-01-191-2/+75
| | | | llvm-svn: 33353
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-3/+0
| | | | llvm-svn: 28378
* Remove PointerType from class TargetEvan Cheng2006-05-171-3/+0
| | | | llvm-svn: 28368
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+51
llvm-svn: 28301
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