bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.	Jim Grosbach	2013-09-04	1	-0/+7
\| \| \| \| \| \| \| \| \| \| \| \| \|	These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972
*	Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵	Craig Topper	2013-07-03	1	-3/+3
\| \| \| \| \| \|	specifying the vector size. llvm-svn: 185540
*	Adding an A15 specific optimization pass for interactions between S/D/Q ↵	Silviu Baranga	2013-03-15	1	-0/+704
	registers. The pass handles all the required transformations pre-regalloc. llvm-svn: 177169