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* AMDGPU: Enable function calls by defaultMatt Arsenault2019-02-281-4/+9
| | | | | | | Fixes some crashes on illegal call situations which are unfortunately still valid IR. llvm-svn: 355051
* AMDGPU: Fix crashes in invalid call casesMatt Arsenault2019-02-282-6/+15
| | | | | | | We have to at least tolerate calls to kernels, possibly with a mismatched calling convention on the callsite. llvm-svn: 355049
* GlobalISel: Implement fewerElementsVector for phiMatt Arsenault2019-02-281-0/+1
| | | | llvm-svn: 355048
* GlobalISel: Implement moreElementsVector for phiMatt Arsenault2019-02-281-0/+1
| | | | llvm-svn: 355047
* [AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operandsDmitry Preobrazhensky2019-02-272-13/+17
| | | | | | | | | | See bug 37943: https://bugs.llvm.org/show_bug.cgi?id=37943 Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D58287 llvm-svn: 354974
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of ↵Dmitry Preobrazhensky2019-02-277-28/+149
| | | | | | | | | | | | instructions s_set_gpr_idx_on and s_set_gpr_idx_mode See bug 39331: https://bugs.llvm.org/show_bug.cgi?id=39331 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D58288 llvm-svn: 354969
* [AMDGPU] Fixed hang during DAG combineStanislav Mekhanoshin2019-02-261-1/+2
| | | | | | | | | | | | | SITargetLowering::reassociateScalarOps() does not touch constants so that DAGCombiner::ReassociateOps() does not revert the combine. However a global address is not a ConstantSDNode. Switched to the method used by DAGCombiner::ReassociateOps() itself to detect constants. Differential Revision: https://reviews.llvm.org/D58695 llvm-svn: 354926
* RegBankSelect: Handle slightly more complex value mappingsMatt Arsenault2019-02-252-8/+47
| | | | | | | | Try to use concat_vectors. Also remove unnecessary assert on pointers. Fixes asserting for <4 x s16> operations and 64-bit pointers for AMDGPU. llvm-svn: 354828
* AMDGPU/GlobalISel: Fix bit ops for non-power-of-2 sizesMatt Arsenault2019-02-251-0/+2
| | | | llvm-svn: 354825
* AMDGPU/GlobalISel: Clamp max implicit_def elementsMatt Arsenault2019-02-251-1/+2
| | | | llvm-svn: 354818
* AMDGPU: Remove IntrReadMem from memtime/memrealtime intrinsicsMatt Arsenault2019-02-251-2/+10
| | | | | | | EarlyCSE with MemorySSA was able to use this to merge multiple calls with no intervening store. llvm-svn: 354814
* AMDGPU: Correct definitions for bitset instructionsMatt Arsenault2019-02-252-13/+21
| | | | | | | These really read and write the result register, so these need a tied input. llvm-svn: 354809
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-2214-137/+138
| | | | | | | It breaks one of our downstream merges, so revert it temporarily while investigating failures downstream llvm-svn: 354700
* AMDGPU: Use removeAllRegUnitsForPhysRegMatt Arsenault2019-02-222-4/+3
| | | | llvm-svn: 354686
* AMDGPU: Remove debugger related subtarget featuresMatt Arsenault2019-02-2117-334/+13
| | | | | | As far as I know these aren't needed anymore. llvm-svn: 354634
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-2114-138/+137
| | | | | | Differential Revision: https://reviews.llvm.org/D58522 llvm-svn: 354620
* [AMDGPU] remove unused AssemblerPredicatesMark Searles2019-02-211-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | An internal build is hitting asserts complaining about too many subtarget features: llvm/utils/TableGen/Types.cpp:42: const char* llvm::getMinimalTypeForEnumBitfield(uint64_t): Assertion `MaxIndex <= 64 && "Too many bits"' failed. llvm/utils/TableGen/AsmMatcherEmitter.cpp:1476: void {anonymous}::AsmMatcherInfo::buildInfo(): Assertion `SubtargetFeatures.size() <= 64 && "Too many subtarget features!"' failed. The short-term solution is to remove a few unused AssemblerPredicates to get under the limit. The long-term solution seems to be to revisit these asserts. E.g., rather than hardcoded '64', use the standard sized std::bitset like the other places that track subtarget features. Differential Revision: https://reviews.llvm.org/D58516 llvm-svn: 354604
* AMDGPU/GlobalISel: Make phis legalMatt Arsenault2019-02-211-0/+13
| | | | llvm-svn: 354592
* AMDGPU/GlobalISel: Fix bit count ops for non-power-of-2 typesMatt Arsenault2019-02-211-1/+3
| | | | llvm-svn: 354587
* [AMDGPU] fix commuted case of sub combineStanislav Mekhanoshin2019-02-211-5/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D58481 llvm-svn: 354543
* AMDGPU/GlobalISel: Move SMRD selection logic to TableGenTom Stellard2019-02-204-128/+136
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: volkan, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52922 llvm-svn: 354516
* GlobalISel: Fix fewerElementsVector for ctlz with different result typeMatt Arsenault2019-02-201-2/+2
| | | | | | Also complete the set of related operations. llvm-svn: 354480
* GlobalISel: Implement moreElementsVector for g_insert resultsMatt Arsenault2019-02-201-14/+24
| | | | llvm-svn: 354477
* GlobalISel: Implement moreElementsVector for selectMatt Arsenault2019-02-191-18/+9
| | | | llvm-svn: 354354
* GlobalISel: Implement moreElementsVector for G_EXTRACT sourceMatt Arsenault2019-02-191-0/+1
| | | | llvm-svn: 354348
* GlobalISel: Implement moreElementsVector for bit opsMatt Arsenault2019-02-191-0/+20
| | | | llvm-svn: 354345
* AMDGPU: Use MachineInstr::mayAlias to replace ↵Changpeng Fang2019-02-182-21/+8
| | | | | | | | | | | | | | | areMemAccessesTriviallyDisjoint in LoadStoreOptimizer pass. Summary: This is to fix a memory dependence bug in LoadStoreOptimizer. Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D58295 llvm-svn: 354295
* GlobalISel: Implement widenScalar for g_extract scalar resultsMatt Arsenault2019-02-181-2/+3
| | | | llvm-svn: 354293
* AMDGPU: Set ABI version to 1 for code object v3Konstantin Zhuravlyov2019-02-143-10/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D57811 llvm-svn: 354085
* GlobalISel: Add alignment to LegalityQuery MMOsMatt Arsenault2019-02-141-9/+10
| | | | | | | This allows targets to specify the minimum alignment required for the load/store. llvm-svn: 354071
* AMDGPU/GlobalISel: Fix RegBankSelect for GEP.Matt Arsenault2019-02-142-32/+15
| | | | | | | | | | This is basically a pointer typed add, so shouldn't be any different. This was assuming everything was an SGPR, which is not true. Also cleanup legality for GEP. I don't seem to be seeing the problem the hack marking s64 as a legal pointer type the comment mentions. llvm-svn: 354067
* [AMDGPU] Ressociate 'add (add x, y), z' to use SALUStanislav Mekhanoshin2019-02-142-0/+44
| | | | | | | | | | | Reassociate adds to collect scalar operands in a single instruction when possible. That will result in a scalar add followed by vector instead of two vector adds, thus better utilizing SALU. Differential Revision: https://reviews.llvm.org/D58220 llvm-svn: 354066
* AMDGPU/GlobalISel: Handle split for 64-bit VALU selectMatt Arsenault2019-02-142-12/+55
| | | | llvm-svn: 354065
* AMDGPU: Try to use function specific STMatt Arsenault2019-02-122-21/+22
| | | | | | | | Subtargets are a function level property, so ideally we would eliminate everywhere that needs to check the global one. Rename the function to try avoiding confusion. llvm-svn: 353900
* AMDGPU: Ignore CodeObjectV3 when inliningMatt Arsenault2019-02-121-0/+1
| | | | | | | | | | This was inhibiting inlining of library functions when clang was invoking the inliner directly. This is covering a bit of a mess with subtarget feature handling, and this shouldn't be a subtarget feature. The behavior is different depending on whether you are using a -mattr flag in clang, or llc, opt. llvm-svn: 353899
* AMDGPU/NFC: Remove SubtargetFeatureISAVersion since it is not used anywhereKonstantin Zhuravlyov2019-02-121-10/+0
| | | | llvm-svn: 353892
* AMDGPU: Remove duplicate processor (gfx900)Konstantin Zhuravlyov2019-02-121-8/+0
| | | | llvm-svn: 353889
* AMDGPU/GlobalISel: Only make f16 constants legal on f16 targetsMatt Arsenault2019-02-121-2/+9
| | | | | | We could deal with it, but there's no real point. llvm-svn: 353845
* GlobalISel: Implement moreElementsVector for implicit_defMatt Arsenault2019-02-111-1/+19
| | | | llvm-svn: 353754
* GlobalISel: Add G_FCANONICALIZE instructionMatt Arsenault2019-02-111-1/+1
| | | | llvm-svn: 353719
* [AMDGPU] Remove unused variableBenjamin Kramer2019-02-111-2/+0
| | | | llvm-svn: 353704
* [AMDGPU] Fix DPP sequence in atomic optimizer.Neil Henning2019-02-111-38/+38
| | | | | | | | | | This commit fixes the DPP sequence in the atomic optimizer (which was previously missing the row_shr:3 step), and works around a read_register exec bug by using a ballot instead. Differential Revision: https://reviews.llvm.org/D57737 llvm-svn: 353703
* [AMDGPU] Enable DPP combiner pass by default.Valery Pykhtin2019-02-111-1/+1
| | | | | | Related revisions: https://reviews.llvm.org/D55444, https://reviews.llvm.org/D55314 llvm-svn: 353691
* [AMDGPU] Split dot-insts featureStanislav Mekhanoshin2019-02-095-24/+56
| | | | | | Differential Revision: https://reviews.llvm.org/D57971 llvm-svn: 353587
* Implementation of asm-goto support in LLVMCraig Topper2019-02-083-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | This patch accompanies the RFC posted here: http://lists.llvm.org/pipermail/llvm-dev/2018-October/127239.html This patch adds a new CallBr IR instruction to support asm-goto inline assembly like gcc as used by the linux kernel. This instruction is both a call instruction and a terminator instruction with multiple successors. Only inline assembly usage is supported today. This also adds a new INLINEASM_BR opcode to SelectionDAG and MachineIR to represent an INLINEASM block that is also considered a terminator instruction. There will likely be more bug fixes and optimizations to follow this, but we felt it had reached a point where we would like to switch to an incremental development model. Patch by Craig Topper, Alexander Ivchenko, Mikhail Dvoretckii Differential Revision: https://reviews.llvm.org/D53765 llvm-svn: 353563
* AMDGPU: Eliminate GPU specific SubtargetFeaturesMatt Arsenault2019-02-084-80/+69
| | | | | | | | | | | Inline compatability is determined from the individual feature bits. These are just sets of the separate features, but will always be treated as incompatible unless they are specifically ignored. Defining the ISA version number here in tablegen would be nice, but it turns out this wasn't actually used. llvm-svn: 353558
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-0815-62/+17
| | | | | | | These are no longer necessary since the R600 tablegen files are split out now. llvm-svn: 353548
* [AMDGPU] Fix CS scratch setup on pre-GCN3 ASICsCarl Ritson2019-02-081-1/+3
| | | | | | | | | | | | | | | | Summary: Prior to GCN3 s_load_dword offsets are in dwords rather than bytes. Thus the scratch buffer descriptor offset must be adjusted for pre-GCN3 ASICs. Reviewers: nhaehnle, tpr Reviewed By: nhaehnle Subscribers: sheredom, arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D56496 llvm-svn: 353530
* AMDGPU/GlobalISel: Fix shift legalization for non-power-of-2Matt Arsenault2019-02-081-0/+2
| | | | | | | | clampScalar doesn't do anything for non-power-of-2 in range. There should probably be a combination rule to reduce the number of matching rules. llvm-svn: 353526
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-086-1/+107
| | | | | | | | | | See bug 39293: https://bugs.llvm.org/show_bug.cgi?id=39293 Reviewers: artem.tamazov, rampitec Differential Revision: https://reviews.llvm.org/D57889 llvm-svn: 353524
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