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* AMDGPU: Whitelist handled intrinsicsMatt Arsenault2016-02-021-8/+36
| | | | | | | We shouldn't crash on unhandled intrinsics. Also simplify failure handling in loop. llvm-svn: 259546
* AMDGPU: Use inbounds when calculating workitem offsetMatt Arsenault2016-02-021-6/+7
| | | | | | | | | | | | | When promoting allocas to LDS, we know we are indexing into a specific area just created, and the calculation will also never overflow. Also emit some of the muls as nsw nuw, because instcombine infers this already from the range metadata. I think putting this on the other adds and muls might be OK too, but I'm not 100% sure. llvm-svn: 259545
* Refactor backend diagnostics for unsupported featuresOliver Stannard2016-02-026-87/+16
| | | | | | | | | | | | | | | | | Re-commit of r258951 after fixing layering violation. The BPF and WebAssembly backends had identical code for emitting errors for unsupported features, and AMDGPU had very similar code. This merges them all into one DiagnosticInfo subclass, that can be used by any backend. There should be minimal functional changes here, but some AMDGPU tests have been updated for the new format of errors (it used a slightly different format to BPF and WebAssembly). The AMDGPU error messages will now benefit from having precise source locations when debug info is available. llvm-svn: 259498
* AMDGPU: Fix emitting invalid workitem intrinsics for HSAMatt Arsenault2016-01-304-34/+219
| | | | | | | | | | | | | | | | | | The AMDGPUPromoteAlloca pass was emitting the read.local.size calls, which with HSA was incorrectly selected to reading from the offset mesa uses off of the kernarg pointer. Error on intrinsics which aren't supported by HSA, and start emitting the correct IR to read the workgroup size out of the dispatch pointer. Also initialize the pass so it can be tested with opt, and start moving towards not depending on the subtarget as an argument. Start emitting errors for the intrinsics not handled with HSA. llvm-svn: 259297
* AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptrMatt Arsenault2016-01-301-9/+4
| | | | | | | | Only the dispatch.ptr intrinsic is supposed to be used now to get the workgroup size, and the read.local.size intrinsics do not work correctly. llvm-svn: 259296
* AMDGPU: Add new amdgcn workitem intrinsicsMatt Arsenault2016-01-302-0/+12
| | | | | | | These use the correct prefix and follow the HSA naming convention rather than the config register option names. llvm-svn: 259293
* AMDGPU: Remove 24-bit intrinsicsMatt Arsenault2016-01-296-53/+0
| | | | | | | The known bit matching code seems to work reasonably well, so these shouldn't really be needed. llvm-svn: 259180
* AMDGPU: Match fmed3 patterns with legacy fmin/fmaxMatt Arsenault2016-01-282-28/+39
| | | | llvm-svn: 259090
* AMDGPU: Match some med3 patternsMatt Arsenault2016-01-289-13/+124
| | | | llvm-svn: 259089
* AMDGPU: Set DX10Clamp bitMatt Arsenault2016-01-281-3/+2
| | | | llvm-svn: 259088
* AMDGPU: waitcnt operand fixesTom Stellard2016-01-283-10/+7
| | | | | | | | | | | | | | | | Summary: Allow lgkmcnt up to 0xF (hardware allows that). Fix mask for ExpCnt in AMDGPUInstPrinter. Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16314 Patch by: Nikolay Haustov llvm-svn: 259059
* AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cppTom Stellard2016-01-286-322/+81
| | | | | | | | | | | | | | Summary: Also delete all the stub functions that are identical to the implementations in TargetInstrInfo.cpp. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16609 llvm-svn: 259054
* Revert r259035, it introduces a cyclic library dependencyOliver Stannard2016-01-286-13/+86
| | | | llvm-svn: 259045
* Add backend dignostic printer for unsupported featuresOliver Stannard2016-01-286-86/+13
| | | | | | | | | | | | | | | | Re-commit of r258951 after fixing layering violation. The related LLVM patch adds a backend diagnostic type for reporting unsupported features, this adds a printer for them to clang. In the case where debug location information is not available, I've changed the printer to report the location as the first line of the function, rather than the closing brace, as the latter does not give the user any information. This also affects optimisation remarks. Differential Revision: http://reviews.llvm.org/D16590 llvm-svn: 259035
* Revert r258951 (and r258950), "Refactor backend diagnostics for unsupported ↵NAKAMURA Takumi2016-01-286-14/+86
| | | | | | | | | | | features" It broke layering violation in LLVMIR. clang r258950 "Add backend dignostic printer for unsupported features" llvm r258951 "Refactor backend diagnostics for unsupported features" llvm-svn: 259016
* Refactor backend diagnostics for unsupported featuresOliver Stannard2016-01-276-86/+14
| | | | | | | | | | | | | | | | | | | | | The BPF and WebAssembly backends had identical code for emitting errors for unsupported features, and AMDGPU had very similar code. This merges them all into one DiagnosticInfo subclass, that can be used by any backend. There should be minimal functional changes here, but some AMDGPU tests have been updated for the new format of errors (it used a slightly different format to BPF and WebAssembly). The AMDGPU error messages will now benefit from having precise source locations when debug info is available. The implementation of DiagnosticInfoUnsupported::print must be in lib/Codegen rather than in the existing file in lib/IR/ to avoid introducing a dependency from IR to CodeGen. Differential Revision: http://reviews.llvm.org/D16590 llvm-svn: 258951
* AMDGPU/SI: Fix commuting of 32-bit VOPC instructionsTom Stellard2016-01-271-2/+4
| | | | | | | | | | | | | | | | Summary: We didn't have entries in the commuting table for the 32-bit instructions. I don't think we hit this problem now, but we will once uniform branching is enabled. Tests will come in a later commit. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16600 llvm-svn: 258936
* AMDGPU/SI: Stoney has only 16 LDS banksMarek Olsak2016-01-272-6/+8
| | | | | | | | | | | | | | Summary: This is a candidate for stable, along with all patches that add the "stoney" processor. Reviewers: tstellarAMD Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16485 llvm-svn: 258922
* Move MCTargetAsmParser.h to llvm/MC/MCParser where it belongs.Benjamin Kramer2016-01-271-5/+5
| | | | llvm-svn: 258917
* AMDGPU: Fix default device handlingMatt Arsenault2016-01-273-11/+17
| | | | | | | | | | | | | | | | | | | When no device name is specified, default to kaveri for HSA since SI is not supported and it woud fail. Default to "tahiti" instead of "SI" since these are effectively the same, and tahiti is an actual device. Move default device handling to the TargetMachine rather than the AMDGPUSubtarget. The module ISA version is computed from the device name provided with the target machine, so the attributes printed by the AsmPrinter were inconsistent with those computed in the subtarget. Also remove DevName field from subtarget since it's redundant with getCPU() in the superclass. llvm-svn: 258901
* [llvm-tblgen] Avoid StringMatcher for GCC and MS builtin namesReid Kleckner2016-01-271-6/+1
| | | | | | | | | | | | | | | This brings the compile time of Function.cpp from ~40s down to ~4s for me locally. It also shaves off about 400KB of object file size in a release+asserts build. I also realized that the AMDGPU backend does not have any GCC builtin names to match, so the extra lookup was a no-op. I removed it to silence a zero-length string table array warning. There should be no functional change here. This change really ends the story of PR11951. llvm-svn: 258897
* [llvm-tblgen] Stop emitting the intrinsic name matching codeReid Kleckner2016-01-261-17/+20
| | | | | | | | | The AMDGPU backend was the last user of the old StringMatcher recognition code. Move it over to the new lookupLLVMIntrinsicName funciton, which is now improved to handle all of the interesting edge cases exposed by AMDGPU intrinsic names. llvm-svn: 258875
* Remove autoconf supportChris Bieneman2016-01-266-100/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* AMDGPU: Move AMDGPU intrinsics only used by R600Matt Arsenault2016-01-262-10/+13
| | | | llvm-svn: 258790
* AMDGPU: Tidy minor td file issuesMatt Arsenault2016-01-264-247/+249
| | | | | | | | | | Make comments and indentation more consistent. Rearrange a few things to be in a more consistent order, such as organizing subtarget features from those describing an actual device property, and those used as options. llvm-svn: 258789
* AMDGPU: Make v32i8/v64i8 illegal typesMatt Arsenault2016-01-264-21/+13
| | | | | | | | Old intrinsics were forcing these, but they have now all been removed. This fixes large i8 vector operations generally being broken. llvm-svn: 258788
* AMDGPU: Remove old sample intrinsicsMatt Arsenault2016-01-264-61/+0
| | | | | | | | | | | I did my best to try to update all the uses in tests that just happened to use the old ones to the newer intrinsics. I'm not sure I got all of the immediate operand conversions correct, since the value seems to have been ignored by the old pattern but I don't think it really matters. llvm-svn: 258787
* AMDGPU: Add new amdgcn intrinsics for cube instructionsMatt Arsenault2016-01-262-5/+9
| | | | | | | More cleanup to try to get all intrinsics using the correct amdgcn prefix that are as close to the instruction as possible. llvm-svn: 258786
* AMDGPU: Implement read_register and write_register intrinsicsMatt Arsenault2016-01-262-0/+50
| | | | | | | | | | | | | | Some of the special intrinsics now that now correspond to a instruction also have special setting of some registers, e.g. llvm.SI.sendmsg sets m0 as well as use s_sendmsg. Using these explicit register intrinsics may be a better option. Reading the exec mask and others may be useful for debugging. For this I'm not sure this is entirely correct because we would want this to be convergent, although it's possible this is already treated sufficently conservatively. llvm-svn: 258785
* AMDGPU: Restore AMDGPU prefixed rsq intrinsic for nowMatt Arsenault2016-01-264-6/+13
| | | | | | Also move into backend intrinsics to discourage use of the old name. llvm-svn: 258783
* AMDGPU: Remove more unused intrinsicsMatt Arsenault2016-01-236-73/+4
| | | | | | Replace tests with lrp with basic IR expansion llvm-svn: 258612
* AMDGPU: Move amdgcn intrinsic handling into SITargetLoweringMatt Arsenault2016-01-232-73/+68
| | | | llvm-svn: 258608
* AMDGPU: Remove IntrNoMem from llvm.SI.sendmsgMatt Arsenault2016-01-231-1/+1
| | | | | | This has side effects. llvm-svn: 258607
* AMDGPU: Remove Feature64BitPtrMatt Arsenault2016-01-233-14/+4
| | | | | | | This is a leftover from AMDIL that doesn't do anything and doesn't belong here. llvm-svn: 258606
* AMDGPU: Add new name for barrier intrinsicMatt Arsenault2016-01-221-1/+7
| | | | llvm-svn: 258558
* AMDGPU: Rename intrinsics to use amdgcn prefixMatt Arsenault2016-01-224-13/+29
| | | | | | | | | | | The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
* AMDGPU: Fix crash with invariant markersMatt Arsenault2016-01-221-0/+8
| | | | | | | | The promote alloca pass didn't handle these intrinsics and crashed. These intrinsics should accept any address space, but for now just erase them to avoid breaking. llvm-svn: 258537
* AMDGPU: Rename some r600 intrinsics to use correct TargetPrefixMatt Arsenault2016-01-223-39/+44
| | | | | | These ones aren't directly emitted by mesa and inserted by a pass. llvm-svn: 258523
* AMDGPU: Remove unused R600 intrinsicsMatt Arsenault2016-01-222-48/+0
| | | | llvm-svn: 258522
* AMDGPU: Change control flow intrinsics to use amdgcn prefixMatt Arsenault2016-01-223-21/+23
| | | | | | | These aren't supposed to be used outside of the backend, so there aren't any users to worry about. llvm-svn: 258516
* AMDGPU: Don't use separate mulhu/mulhs PatsMatt Arsenault2016-01-221-12/+2
| | | | llvm-svn: 258515
* AMDGPU: Remove random TGSI intrinsicMatt Arsenault2016-01-223-14/+0
| | | | | | I don't think this was ever used. llvm-svn: 258514
* AMDGPU: Remove AMDGPU.fract intrinsicMatt Arsenault2016-01-224-7/+1
| | | | | | | Mesa doesn't use this, and this is pattern matched already from fsub x, (ffloor x) llvm-svn: 258513
* AMDGPU/SI: Pass whether to use the SI scheduler via Target AttributeTom Stellard2016-01-214-1/+13
| | | | | | | | | | | | | | | | Summary: Currently the SI scheduler can be selected via command line option, but it turned out it would be better if it was selectable via a Target Attribute. This patch adds "si-scheduler" attribute to the backend. Reviewers: tstellarAMD, echristo Subscribers: echristo, arsenm Differential Revision: http://reviews.llvm.org/D16192 llvm-svn: 258386
* AMDGPU/SI: Promote i1 SETCC operationsTom Stellard2016-01-201-0/+1
| | | | | | | | | | | | | | Summary: While working on uniform branching, I've hit a few cases where we emit i1 SETCC operations. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16233 llvm-svn: 258352
* AMDGPU: Fix old comments that mention AMDILMatt Arsenault2016-01-203-4/+4
| | | | llvm-svn: 258350
* AMDGPU: Remove AMDGPU.trunc intrinsicMatt Arsenault2016-01-202-3/+0
| | | | llvm-svn: 258348
* AMDGPU: Remove AMDIL.fraction intrinsicMatt Arsenault2016-01-203-4/+1
| | | | llvm-svn: 258347
* AMDGPU: Remove AMDIL.round.nearest intrinsicMatt Arsenault2016-01-202-3/+0
| | | | llvm-svn: 258346
* AMDGPU: Remove abs intrinsicMatt Arsenault2016-01-203-16/+0
| | | | llvm-svn: 258343
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