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* AMDGPU/SI: Update LiveIntervals during SIFixSGPRLiveRangesMatt Arsenault2015-08-151-4/+13
| | | | | | | | | Does not mark SlotIndexes as reserved, although I think that might be OK. LiveVariables still need to be handled. llvm-svn: 245133
* AMDGPU: Remove unnecessary assertMatt Arsenault2015-08-151-1/+1
| | | | | | | These shouldn't ever be null. The number of successors was already asserted to be 2. llvm-svn: 245132
* AMDGPU/SI: Make comments more precise.Matt Arsenault2015-08-151-8/+8
| | | | | | | | | | | True branch instructions do behave as expected with liveness. Avoid the phrasing "branch decision is based on a value in an SGPR" because this could be misleading. A VALU compare instruction's result is still based on an SGPR, even though that condition may be divergent. llvm-svn: 245131
* AMDGPU/SI: Add missing spill classTom Stellard2015-08-141-1/+2
| | | | | | | | The compiler was failing to spill for some shaders. Patch By: Axel Davy llvm-svn: 245087
* [AMDGPU] Use the general SMAX/SMIN/UMAX/UMIN pattern matching and remove the ↵Simon Pilgrim2015-08-132-53/+0
| | | | | | | | | | AMDGPU implementation D9746 added general SMAX/SMIN/UMAX/UMIN pattern matching to SelectionDAGBuilder::visitSelect. Differential Revision: http://reviews.llvm.org/D12007 llvm-svn: 244960
* Remove and forbid raw_svector_ostream::flush() calls.Yaron Keren2015-08-131-2/+0
| | | | | | | | | | After r244870 flush() will only compare two null pointers and return, doing nothing but wasting run time. The call is not required any more as the stream and its SmallString are always in sync. Thanks to David Blaikie for reviewing. llvm-svn: 244928
* AMDGPU: Fix assert on dbg_value instructionsMatt Arsenault2015-08-121-0/+6
| | | | llvm-svn: 244728
* PseudoSourceValue: Replace global manager with a manager in a machine function.Alex Lorenz2015-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | This commit removes the global manager variable which is responsible for storing and allocating pseudo source values and instead it introduces a new manager class named 'PseudoSourceValueManager'. Machine functions now own an instance of the pseudo source value manager class. This commit also modifies the 'get...' methods in the 'MachinePointerInfo' class to construct pseudo source values using the instance of the pseudo source value manager object from the machine function. This commit updates calls to the 'get...' methods from the 'MachinePointerInfo' class in a lot of different files because those calls now need to pass in a reference to a machine function to those methods. This change will make it easier to serialize pseudo source values as it will enable me to transform the mips specific MipsCallEntry PseudoSourceValue subclass into two target independent subclasses. Reviewers: Akira Hatanaka llvm-svn: 244693
* Fix some comment typos.Benjamin Kramer2015-08-084-9/+9
| | | | llvm-svn: 244402
* AMDGPU/SI: Another attempt to fix Windows bots broken by r244372Tom Stellard2015-08-081-1/+1
| | | | llvm-svn: 244383
* AMDGPU: Implement AMDGPUOperand::print()Matt Arsenault2015-08-081-1/+16
| | | | llvm-svn: 244381
* AMDGPU/SI: Remove VCCRegMatt Arsenault2015-08-086-31/+48
| | | | llvm-svn: 244380
* AMDGPU/SI: Remove source uses of VCCRegMatt Arsenault2015-08-084-15/+38
| | | | llvm-svn: 244379
* AMDGPU/SI: Attempt to fix Windows bots broken by r244372Tom Stellard2015-08-081-1/+1
| | | | llvm-svn: 244376
* AMDGPU: Add pass to lower OpenCL image and sampler arguments.Tom Stellard2015-08-074-0/+373
| | | | | | | | | The pass adds new kernel arguments for image attributes, and resolves calls to dummy attribute and resource id getter functions. Patch by: Zoltan Gilian llvm-svn: 244372
* AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructionsTom Stellard2015-08-072-14/+38
| | | | | | | | | | | | | | | | Summary: With InstAlias, we don't need to print the _e32 portion of the mnemonic when we print the $dst operand. This change makes it possible to include vcc in the asm string when we switch VOPC over to having implicit vcc defs. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11813 llvm-svn: 244362
* AMDGPU: Assume SMRD access for constant address spaceMatt Arsenault2015-08-072-40/+76
| | | | | | | Since r243294 these are selected to SMRD and moved later if required. llvm-svn: 244354
* AMDGPU/SI: Use correct encoding of vopc for VI in the assemblerTom Stellard2015-08-071-0/+2
| | | | | | | | | | | | Summary: We were using the SI encoding for VI. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11812 llvm-svn: 244332
* AMDGPU/SI: v_mac_legacy_f32 does not exist on VITom Stellard2015-08-071-6/+6
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11810 llvm-svn: 244322
* AMDGPU/SI: Remove unused outs parameter from VOPC TableGen classesTom Stellard2015-08-071-5/+5
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11809 llvm-svn: 244321
* AMDGPU/SI: Add Fiji supportTom Stellard2015-08-061-0/+4
| | | | | | Patch by: Alex Deucher llvm-svn: 244255
* AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CITom Stellard2015-08-065-20/+115
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11604 llvm-svn: 244254
* AMDGPU/SI: Use ComplexPatterns for SMRD addressing modesTom Stellard2015-08-064-54/+127
| | | | | | | | | | | | Summary: This allows us to consolidate several of the TableGen patterns. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11602 llvm-svn: 244253
* AMDGPU/SI: Remove EXECRegMatt Arsenault2015-08-055-21/+9
| | | | | | For the same reasons as the other physical registers. llvm-svn: 244062
* AMDGPU: Remove SCCReg.Matt Arsenault2015-08-055-36/+22
| | | | | | | These should be handled as a physical register rather than a virtual register class with one member. llvm-svn: 244061
* De-constify pointers to Type since they can't be modified. NFCCraig Topper2015-08-012-4/+4
| | | | | | This was already done in most places a while ago. This just fixes the ones that crept in over time. llvm-svn: 243842
* AMDGPU/SI: Add implicit register operands in the correct order.Alex Lorenz2015-07-312-21/+1
| | | | | | | | | | | | | | | | | | This commit fixes a bug in the class 'SIInstrInfo' where the implicit register machine operands were added to a machine instruction in an incorrect order - the implicit uses were added before the implicit defs. I found this bug while working on moving the implicit register operand verification code from the MIR parser to the machine verifier. This commit also makes the method 'addImplicitDefUseOperands' in the machine instruction class public so that it can be reused in the 'SIInstrInfo' class. Reviewers: Matt Arsenault Differential Revision: http://reviews.llvm.org/D11689 llvm-svn: 243799
* AMDGPU: Fix v16i32 to v16i8 truncstoreMatt Arsenault2015-07-311-0/+1
| | | | llvm-svn: 243731
* AMDGPU/SI: Set DwarfRegNumMatt Arsenault2015-07-311-6/+14
| | | | | | | This requires a fix in tablegen for the cast<int> from bits<16> to work in the list initializer. llvm-svn: 243723
* AMDGPU/SI: Remove unused pattern for f32 constant loadsTom Stellard2015-07-311-1/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11603 llvm-svn: 243719
* AMDGPU: Set SubRegIndex size and offsetMatt Arsenault2015-07-301-2/+1
| | | | | | | | I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission. llvm-svn: 243661
* AMDGPU: Fix unreachable when emitting binary debug infoMatt Arsenault2015-07-301-1/+33
| | | | | | | | | | | Copy implementation of applyFixup from AArch64 with AArch64 bits ripped out. Tests will be included with a later commit. Several other problems must be fixed before binary debug info emission will work. llvm-svn: 243660
* AMDGPU/SI: Simplify moveSMRDToVALU()Tom Stellard2015-07-301-11/+9
| | | | | | | | | | | | | | | Summary: Replace the switch on instruction opcode with a switch on register size. This way we don't need to update the switch statement when we add new SMRD variants. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11601 llvm-svn: 243652
* AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfoTom Stellard2015-07-302-15/+0
| | | | | | | | | | | | | | Summary: This function is never called. isReallyTriviallyReMaterializable() is the function that should be implemented instead. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11620 llvm-svn: 243651
* Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all ↵Nick Lewycky2015-07-291-1/+1
| | | | | | | | the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.) Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h. llvm-svn: 243585
* Fix broken ArrayRef conversion from r243497.Alex Lorenz2015-07-281-1/+1
| | | | llvm-svn: 243501
* MIR Serialization: Serialize the target index machine operands.Alex Lorenz2015-07-282-0/+14
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243497
* AMDGPU: Don't try to use LDS/vector for private if pointer value storedMatt Arsenault2015-07-281-4/+14
| | | | | | | If the pointer is the store's value operand, this would produce a broken module. Make sure the use is actually for the pointer operand. llvm-svn: 243462
* AMDGPU: Fix crash if called function is a bitcastMatt Arsenault2015-07-281-1/+6
| | | | | | | getCalledFunction() is null, so this would crash. Replace crash with an error on unsupported call. llvm-svn: 243461
* AMDGPU: Fix return type of getImplicitParameterOffset.Matt Arsenault2015-07-281-1/+1
| | | | | | Patch by Zoltan Gilian <zoltan.gilian@gmail.com> llvm-svn: 243459
* [llvm-mc] Pushing plumbing through for --fatal-warnings flag.Colin LeMahieu2015-07-271-1/+1
| | | | llvm-svn: 243334
* AMDGPU: don't match vgpr loads for constant loadsMarek Olsak2015-07-271-3/+0
| | | | | | | | | | | | Author: Dave Airlie <airlied@redhat.com> In order to implement indirect sampler loads, we don't want to match on a VGPR load but an SGPR one for constants, as we cannot feed VGPRs to the sampler only SGPRs. this should be applicable for llvm 3.7 as well. llvm-svn: 243294
* AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaroundMarek Olsak2015-07-271-2/+2
| | | | | | This is a candidate for 3.7. llvm-svn: 243263
* [PM/AA] Remove all of the dead AliasAnalysis pointers being threadedChandler Carruth2015-07-221-2/+1
| | | | | | | | | | through APIs that are no longer necessary now that the update API has been removed. This will make changes to the AA interfaces significantly less disruptive (I hope). Either way, it seems like a really nice cleanup. llvm-svn: 242882
* AMDGPU: Set isMoveImm on s_movk_i32Matt Arsenault2015-07-211-1/+1
| | | | llvm-svn: 242747
* AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory opsTom Stellard2015-07-204-6/+70
| | | | | | | | | | | | | | Summary: The MUBUF addr64 bit has been removed on VI, so we must use FLAT instructions when the pointer is stored in VGPRs. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11067 llvm-svn: 242673
* Remove TargetInstrInfo::canFoldMemoryOperandSimon Pilgrim2015-07-192-7/+0
| | | | | | | | | | canFoldMemoryOperand is not actually used anywhere in the codebase - all existing users instead call foldMemoryOperand directly when they wish to fold and can correctly deduce what they need from the return value. This patch removes the canFoldMemoryOperand base function and the target implementations; only x86 had a real (bit-rotted) implementation, although AMDGPU had a preparatory stub that had never needed to be completed. Differential Revision: http://reviews.llvm.org/D11331 llvm-svn: 242638
* AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operandTom Stellard2015-07-161-6/+9
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11226 llvm-svn: 242434
* AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsetsTom Stellard2015-07-164-3/+39
| | | | | | | | | | | | | | Summary: We can safely assume that the high bit of scratch offsets will never be set, because this would require at least 128 GB of GPU memory. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11225 llvm-svn: 242433
* AMDGPU/R600: Remove unused variableTom Stellard2015-07-161-1/+0
| | | | | | This fixes a warning introduced by r242410. llvm-svn: 242412
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