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* [AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton2017-05-265-31/+113
* Revert r303859, CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll fails on bots.Nico Weber2017-05-251-3/+1
* [AMDGPU] add intrinsic for s_getpcTim Corringham2017-05-251-1/+3
* [AMDGPU] Prevent too large store merges in AMDGPU Subtargets. NFCI.Nirav Dave2017-05-244-0/+24
* Revert "AMDGPU: Fold CI-specific complex SMRD patterns into existing complex ...Marek Olsak2017-05-244-18/+51
* [AMDGPU] Add INDIRECT_BASE_ADDR to R600_Reg32 class (PR33045)Simon Pilgrim2017-05-231-1/+1
* AMDGPU/SI: Move the local memory usage related checking after calling convent...Changpeng Fang2017-05-231-99/+114
* [AMDGPU] Combine and (srl) into shl (bfe)Stanislav Mekhanoshin2017-05-233-11/+40
* AMDGPU: Fold CI-specific complex SMRD patterns into existing complex patternsMarek Olsak2017-05-234-51/+18
* [AMDGPU] Convert shl (add) into add (shl)Stanislav Mekhanoshin2017-05-232-2/+43
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-2313-64/+552
* [AMDGPU] Narrow lshl from 64 to 32 bit if possibleStanislav Mekhanoshin2017-05-221-11/+33
* [AMDGPU] Fix incorrect register usage tracking in GCNUpwardTrackerValery Pykhtin2017-05-222-62/+86
* [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literalsDmitry Preobrazhensky2017-05-192-4/+12
* [AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky2017-05-192-10/+31
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-1812-83/+86
* [AMDGPU] SDWA operands should not intersect with potential MIsSam Kolton2017-05-181-13/+32
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-1722-116/+461
* AMDGPU: Expand frame indexes to be relative to scratch wave offsetMatt Arsenault2017-05-171-6/+71
* AMDGPU: Change mubuf soffset register when SP relativeMatt Arsenault2017-05-172-15/+53
* AMDGPU: Make better use of op_sel with high componentsMatt Arsenault2017-05-172-8/+57
* AMDGPU: Try to use op_sel when selecting packed instructionsMatt Arsenault2017-05-171-1/+29
* AMDGPU: Use appropriate soffset for spillingMatt Arsenault2017-05-172-20/+20
* AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault2017-05-173-2/+25
* [AMDGPU] Use GCNRPTracker dumper methods in schedulerStanislav Mekhanoshin2017-05-163-18/+21
* [AMDGPU] Cache live-ins and register pressure in schedulerStanislav Mekhanoshin2017-05-162-75/+154
* [AMDGPU] Turn register pressure estimation into forward trackerStanislav Mekhanoshin2017-05-164-135/+196
* AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]NAKAMURA Takumi2017-05-162-2/+4
* [AMDGPU] Kill now unused phiInfoElementGetDebugLoc(). NFCI.Davide Italiano2017-05-151-5/+0
* Re-submit AMDGPUMachineCFGStructurizer.Jan Sjodin2017-05-157-12/+3245
* Revert 303091.Jan Sjodin2017-05-157-3380/+12
* Add AMDGPUMachineCFGStructurizer.Jan Sjodin2017-05-157-12/+3380
* [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64Dmitry Preobrazhensky2017-05-151-11/+22
* [AMDGPU][MC] Removed V_MQSAD_U16_U8Dmitry Preobrazhensky2017-05-151-3/+0
* AMDGPU/SI: Don't promote to vector if the load/store is volatile.Changpeng Fang2017-05-121-2/+5
* [KnownBits] Add bit counting methods to KnownBits struct and use them where p...Craig Topper2017-05-121-1/+1
* AMDGPU/GlobalISel: Mark 32-bit integer constants as legalTom Stellard2017-05-121-0/+1
* [AMDGPU] Placate unused variable warning in release builds.Davide Italiano2017-05-111-0/+1
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-113-23/+22
* AMDGPU: Pull fneg out of extract_vector_eltMatt Arsenault2017-05-114-1/+31
* [AMDGPU] Fix incorrect register pressure calculationStanislav Mekhanoshin2017-05-111-2/+3
* Remove now useless trailing nullptr in StructType::getSerge Guelton2017-05-111-1/+1
* AMDGPU: Make some packed shuffles freeMatt Arsenault2017-05-102-1/+36
* AMDGPU: Add new subtarget features for gfx9 flat instructionsMatt Arsenault2017-05-103-1/+38
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler...Dmitry Preobrazhensky2017-05-101-6/+12
* [AMDGPU] Fixed typo in GCNRegPressure, NFCStanislav Mekhanoshin2017-05-092-15/+15
* [RegisterBankInfo] Uniquely allocate instruction mapping.Quentin Colombet2017-05-052-47/+49
* [AMDGPU] In the new waitcnt insertion pass, use getHeader Kannan Narayanan2017-05-051-5/+5
* AMDGPU/AMDHSA: Set COMPUTE_PGM_RSRC2:LDS_SIZE to 0Konstantin Zhuravlyov2017-05-051-1/+2
* [KnownBits] Add wrapper methods for setting and clear all bits in the underly...Craig Topper2017-05-051-1/+1
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