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* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-058-57/+162
| | | | | | | | dependent instruction selection. Differential revision: https://reviews.llvm.org/D35267 llvm-svn: 326703
* AMDGPU/GlobalISel: InstrMapping for G_ZEXTMatt Arsenault2018-03-021-0/+20
| | | | llvm-svn: 326589
* AMDGPU/GlobalISel: InstrMapping for G_TRUNCMatt Arsenault2018-03-021-0/+10
| | | | llvm-svn: 326588
* AMDGPU/GlobalISel: Define InstrMappings for G_FCMPMatt Arsenault2018-03-021-0/+9
| | | | | | Patch by Tom Stellard llvm-svn: 326587
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnumMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326586
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnumMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326567
* AMDGPU/GCN: Promote i16 ctpopJan Vesely2018-03-022-0/+5
| | | | | | | | | i16 capable ASICs do not support i16 operands for this instruction. Add tablegen pattern to merge chained i16 additions. Differential Revision: https://reviews.llvm.org/D43985 llvm-svn: 326535
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSIMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326534
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUIMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326533
* AMDGPU/GlobalISel: Define instruction mapping for G_FMULMatt Arsenault2018-03-021-0/+1
| | | | llvm-svn: 326532
* AMDGPU/GlobalISel: Define instruction mapping for G_FADDMatt Arsenault2018-03-021-1/+3
| | | | | | Patch by Tom Stellard llvm-svn: 326526
* AMDGPU/GlobalISel: Define instruction mapping for G_SHLMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326525
* AMDGPU/GlobalISel: Define instruction mapping for G_XORMatt Arsenault2018-03-021-0/+1
| | | | llvm-svn: 326524
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326523
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-011-1/+13
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-012-0/+57
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* AMDGPU/GlobalISel: Remove default register mappingMatt Arsenault2018-03-011-16/+1
| | | | | | | | | This crashes for some opcodes, which prevents the SelectionDAG fallback from working. Patch by Tom Stellard llvm-svn: 326487
* AMDGPU/GlobalISel: Use a more correct getValueMappingMatt Arsenault2018-03-011-19/+56
| | | | | | | | | This was finding the wrong size registers for anything with more than 2 components. Patch by Tom Stellard llvm-svn: 326483
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-011-0/+6
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: Mark i32->i64 zext as legalMatt Arsenault2018-03-011-0/+3
| | | | llvm-svn: 326481
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-011-4/+16
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-011-1/+21
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-014-15/+101
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Make i32 mul legalMatt Arsenault2018-03-011-0/+1
| | | | llvm-svn: 326471
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-012-0/+8
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-011-0/+1
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Add copyCost for VGPR->SGPR copiesMatt Arsenault2018-03-011-4/+7
| | | | | | Patch by Tom Stellard llvm-svn: 326467
* AMDGPU/GlobalISel: Make i32 xor legalMatt Arsenault2018-03-011-2/+2
| | | | llvm-svn: 326466
* AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legalMatt Arsenault2018-03-011-0/+4
| | | | | | Patch by Tom Stellard llvm-svn: 326465
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legalMatt Arsenault2018-03-011-0/+3
| | | | | | Patch by Tom Stellard llvm-svn: 326464
* [AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not foundAlexander Timofeev2018-03-011-1/+7
| | | | | | Differential revision: https://reviews.llvm.org./D43334 llvm-svn: 326451
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-283-7/+47
| | | | | | | | | | | | | | | | | Summary: For use by LLPC SPV_AMD_shader_ballot extension. The v_writelane instruction was already implemented for use by SGPR spilling, but I had to add an extra dummy operand tied to the destination, to represent that all lanes except the selected one keep the old value of the destination register. .ll test changes were due to schedule changes caused by that new operand. Differential Revision: https://reviews.llvm.org/D42838 llvm-svn: 326353
* AMDGPU: Add fast fmaf feature to gfx702Konstantin Zhuravlyov2018-02-271-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D43790 llvm-svn: 326252
* AMDGPU/GlobalISel: Make f64 constants legalMatt Arsenault2018-02-261-0/+1
| | | | llvm-svn: 326101
* [AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shaderTim Renouf2018-02-262-1/+20
| | | | | | | | | | | | | | | | Summary: With OS type AMDPAL, the scratch descriptor is hardwired to be loaded from offset 0 of the global information table, whose low pointer is passed in s0. For a merge shader on gfx9+, it needs to be s8 instead, as the hardware reserves s0-s7. Reviewers: kzhuravl Subscribers: arsenm, nhaehnle, dstuttard, llvm-commits, t-tye, yaxunl, wdng, kzhuravl Differential Revision: https://reviews.llvm.org/D42203 llvm-svn: 326088
* [AMDGPU] Shrinking V_SUBBREV_U32Stanislav Mekhanoshin2018-02-241-1/+2
| | | | | | | | | | V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when we try to commute V_SUBB_U32 in order to shrink it we do not then process V_SUBBREV_U32 and it stay VOP3. This is fixed. Differential Revision: https://reviews.llvm.org/D43699 llvm-svn: 326011
* Fix compiler warning introduced in r325931. NFC.Geoff Berry2018-02-231-3/+2
| | | | llvm-svn: 325938
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-235-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* AMDGPU: Track physreg uses in SILoadStoreOptimizerNicolai Haehnle2018-02-231-32/+32
| | | | | | | | | | | | | | | | Summary: This handles def-after-use of physregs, and allows us to merge loads and stores even across some physreg defs (typically M0 defs). Change-Id: I076484b2bda27c2cf46013c845a0380c5b89b67b Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D42647 llvm-svn: 325882
* AMDGPU: Stop using .NAME in .td filesNicolai Haehnle2018-02-221-6/+6
| | | | | | | | | | | | | | | | | | | Summary: .NAME is a bit of an odd duck, in that we should really treat it like a template argument, but we currently don't, and so when and where NAME is initialized and how is pretty inconsistent. Best to just avoid using it as a field of already instantiated records, and use cast to string instead. Change-Id: I5a0c202401cede3d5c3827ab9c7858ea48b29108 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D43551 llvm-svn: 325794
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-02-221-1/+1
| | | | | | "a a" -> "a" llvm-svn: 325752
* AMDGPU: Do not combine loads/store across physreg defsNicolai Haehnle2018-02-211-1/+19
| | | | | | | | | | | | | | | | | | | Summary: Since this pass operates on machine SSA form, this should only really affect M0 in practice. Fixes various piglit variable-indexing/vs-varying-array-mat4-index-* Change-Id: Ib2a1dc3a8d7b08225a8da49a86f533faa0986aa8 Fixes: r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4") Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D40343 llvm-svn: 325677
* [AMDGPU][MC] Added lds support for MUBUF instructionsDmitry Preobrazhensky2018-02-214-54/+168
| | | | | | | | | See bug 28234: https://bugs.llvm.org/show_bug.cgi?id=28234 Differential Revision: https://reviews.llvm.org/D43472 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 325676
* Revert "[AMDGPU] Increased vector length for global/constant loads."Konstantin Zhuravlyov2018-02-202-34/+2
| | | | | | | | | | https://reviews.llvm.org/rL325518 It breaks following OpenCL conformance tests: - Basic - parameter_types - Basic - vload_private llvm-svn: 325643
* [AMDGPU] stop buffer_store being moved illegallyTim Renouf2018-02-201-6/+2
| | | | | | | | | | | | | | | Summary: The machine instruction scheduler was illegally moving a buffer store past a buffer load with the same descriptor and offset. Fixed by marking buffer ops as mayAlias and isAliased. This may be overly conservative, and we may need to revisit. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D43332 Change-Id: Iff3173d9e0653e830474546276ab9d30318b8ef7 llvm-svn: 325567
* [AMDGPU] Make note of existing waitcnt instrs; this is add-on work related ↵Mark Searles2018-02-191-18/+16
| | | | | | to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up. llvm-svn: 325524
* [AMDGPU] Increased vector length for global/constant loads.Mark Searles2018-02-192-2/+34
| | | | | | | | | | | | | | Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D43275 llvm-svn: 325518
* [AMDGPU] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-171-0/+2
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Stanislav Mekhanoshin, Tom Stellard. llvm-svn: 325425
* AMDGPU: Remove unused private member of AMDGPUTargetELFStreamerKonstantin Zhuravlyov2018-02-162-2/+1
| | | | llvm-svn: 325408
* Remove an unused function.Eric Christopher2018-02-161-4/+0
| | | | llvm-svn: 325403
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