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* [AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. ...Sam Kolton2016-04-062-11/+54
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-061-1/+1
* [AMDGPU] Emit linkonce and linkonce_odr symbolsKonstantin Zhuravlyov2016-04-051-0/+2
* AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}Tom Stellard2016-04-018-3/+117
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-012-8/+8
* [AMDGPU] Disassembler: support for DPPSam Kolton2016-03-312-7/+23
* AMDGPU: Add frexp_exp intrinsicMatt Arsenault2016-03-301-2/+2
* Silencing warnings from MSVC 2015 Update 2. All of these changes silence "C43...Aaron Ballman2016-03-302-3/+3
* AMDGPU/SI: Improve MachineSchedModel definitionTom Stellard2016-03-301-19/+27
* AMDGPU/SI: Enable lanemask tracking in mischedTom Stellard2016-03-301-0/+4
* Test commit accessKonstantin Zhuravlyov2016-03-291-1/+1
* AMDGPU/SI: Limit load clustering to 16 bytes instead of 4 instructionsTom Stellard2016-03-281-8/+33
* AMDGPU: Fix a use-after free and a missing breakJustin Bogner2016-03-251-1/+2
* AMDGPU: Cost model for basic integer operationsMatt Arsenault2016-03-251-0/+31
* AMDGPU: Partially implement getArithmeticInstrCost for FP opsMatt Arsenault2016-03-252-1/+94
* AMDGPU: TTI: Make insertelement free.Matt Arsenault2016-03-251-0/+5
* AMDGPU/SI: Add Polaris supportTom Stellard2016-03-241-0/+8
* Fix sequence point warning. NFC.Vasileios Kalintiris2016-03-241-1/+1
* AMDGPU: Remove atomic inc/dec patternsMatt Arsenault2016-03-231-23/+0
* AMDGPU: Promote alloca should skip volatilesMatt Arsenault2016-03-231-0/+13
* AMDGPU: Insert moves of frame index to value operandsMatt Arsenault2016-03-231-0/+56
* [AMDGPU] Fix missing assembler predicates.Valery Pykhtin2016-03-231-0/+4
* AMDGPU: Cache information about register pressure setsTom Stellard2016-03-232-24/+37
* AMDGPU: Fix dangling references introduced by r263982Nicolai Haehnle2016-03-211-3/+5
* AMDGPU: Coding style fixesNicolai Haehnle2016-03-211-4/+2
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-219-15/+515
* AMDGPU/SI: Fix threshold calculation for branching when exec is zeroTom Stellard2016-03-211-3/+5
* AMDGPU: Remove SignBitIsZero for mubuf scratch offsetsMatt Arsenault2016-03-211-1/+1
* AMDGPU: Add frexp_mant intrinsicMatt Arsenault2016-03-211-2/+2
* AMDGPU: add missing braces around multi-line if blockNicolai Haehnle2016-03-181-1/+2
* AMDGPU: Overload return type of llvm.amdgcn.buffer.load.formatNicolai Haehnle2016-03-181-36/+43
* AMDGPU/SI: Add llvm.amdgcn.buffer.atomic.* intrinsicsNicolai Haehnle2016-03-183-2/+187
* AMDGPU: use ComplexPattern for offsets in llvm.amdgcn.buffer.load/store.formatNicolai Haehnle2016-03-183-13/+110
* [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3Sam Kolton2016-03-182-50/+95
* AMDGPU/SI: Do not generate s_waitcnt after ds_permute/ds_bpermuteChangpeng Fang2016-03-171-1/+1
* AMDGPU: mark atomic instructions as sources of divergenceNicolai Haehnle2016-03-171-0/+7
* AMDGPU: Prevent uniform loops from becoming infiniteNicolai Haehnle2016-03-161-0/+6
* AMDGPU: Verify instructions in non-debug builds as wellMichel Danzer2016-03-161-3/+3
* AMDGPU/SI: Clean up indentation in SIInstrInfo::getDefaultRsrcDataFormatMichel Danzer2016-03-161-3/+3
* AMDGPU/SI: Implement GroupStaticSize Intrinsic for Dynamic LDSChangpeng Fang2016-03-152-2/+19
* [DAG] use isUndef() ; NFCISanjay Patel2016-03-141-4/+4
* AMDGPU/SI: Handle wait states required for DPP instructionsTom Stellard2016-03-142-0/+63
* AMDGPU/SI: Incomplete shader binaries need to finish execution at the endMarek Olsak2016-03-142-8/+24
* AMDGPU: mark llvm.amdgcn.image.atomic.* as a source of divergenceNicolai Haehnle2016-03-141-0/+13
* [AMDGPU] Assembler: SOP* instruction fixesNikolay Haustov2016-03-142-27/+40
* [AMDGPU] AsmParser: Factor out parseRegister. NFC.Valery Pykhtin2016-03-141-24/+40
* [AMDGPU] AsmParser: refactor post push_back vector access. NFC.Valery Pykhtin2016-03-141-6/+5
* [AMDGPU] AsmParser: remove redundant isReg checks. NFC.Valery Pykhtin2016-03-141-7/+7
* [AMDGPU] Fix VOPC instruction operand namingsValery Pykhtin2016-03-111-2/+2
* [AMDGPU] Assembler: change v_madmk operands to have same order as mad.Nikolay Haustov2016-03-114-28/+19
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