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* [AMDGPU] Force qsads instrs to use different dest register than source registersMark Searles2017-06-081-0/+5
| | | | | | | | The V_MQSAD_PK_U16_U8, V_QSAD_PK_U16_U8, and V_MQSAD_U32_U8 take more than 1 pass in hardware. For these three instructions, the destination registers must be different than all sources, so that the first pass does not overwrite sources for the following passes. Differential Revision: https://reviews.llvm.org/D33783 llvm-svn: 304998
* [AMDGPU] V_DIV_FIXUP_F16 is not a commutable operationStanislav Mekhanoshin2017-06-031-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D33808 llvm-svn: 304619
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-4/+5
| | | | | | | | | | | | | | | Summary: Added separate pseudo and real instruction for GFX9 SDWA instructions. Currently supports only in assembler. Depends D32493 Reviewers: vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33132 llvm-svn: 303620
* AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault2017-05-171-1/+19
| | | | | | Fix missing instruction definitions for min3/max3. llvm-svn: 303284
* [AMDGPU][MC] Removed V_MQSAD_U16_U8Dmitry Preobrazhensky2017-05-151-3/+0
| | | | | | | | | | | | This instruction does not really exist See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018 Reviewers: vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D33126 llvm-svn: 303055
* [AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)Dmitry Preobrazhensky2017-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | Added support for VI: - s_endpgm_saved - s_wakeup - s_rfe_restore_b64 - v_perm_b32 Enabled for VI: - v_mov_fed_b32 - v_mov_fed_b32_e64 See bug 32593: https://bugs.llvm.org//show_bug.cgi?id=32593 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D31931 llvm-svn: 300076
* [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CIDmitry Preobrazhensky2017-04-121-1/+1
| | | | | | | | | | | | Corrected encoding of V_MQSAD_U32_U8 for CI See bug 32552: https://bugs.llvm.org//show_bug.cgi?id=32552 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31810 llvm-svn: 300070
* [AMDGPU][MC] Fix for Bug 28204 + LIT testsDmitry Preobrazhensky2017-03-221-8/+22
| | | | | | | | | | Fixed v_mad_i64_i32/u64_u32 encoding Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30828 llvm-svn: 298502
* AMDGPU: Add definition for v_xad_u32Matt Arsenault2017-02-281-0/+2
| | | | llvm-svn: 296515
* AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault2017-02-271-4/+12
| | | | llvm-svn: 296401
* AMDGPU: Add some of the new gfx9 VOP3 instructionsMatt Arsenault2017-02-271-0/+12
| | | | llvm-svn: 296382
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-0/+26
| | | | | | | | Add a few non-VOP3P but instructions related to packed. Includes hack with dummy operands for the benefit of the assembler llvm-svn: 296368
* AMDGPU: Remove modifiers from v_div_scale_*Matt Arsenault2017-01-191-1/+5
| | | | | | | | They seem to produce nonsense results when used. This should be applied to the release branch. llvm-svn: 292472
* [AMDGPU] Handle f16 select{_cc}Konstantin Zhuravlyov2016-11-161-5/+0
| | | | | | | | | | - Select `select` to `v_cndmask_b32` - Expand `select_cc` - Refactor patterns Differential Revision: https://reviews.llvm.org/D26714 llvm-svn: 287074
* AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*Matt Arsenault2016-11-151-0/+2
| | | | | | | This doesn't solve any problems I know about, but this should have more conservative assumptions about the operands' llvm-svn: 286913
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-4/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D25975 llvm-svn: 286753
* AMDGPU: Add VI i16 supportTom Stellard2016-11-101-0/+32
| | | | | | | | Patch By: Wei Ding Differential Revision: https://reviews.llvm.org/D18049 llvm-svn: 286464
* Revert "AMDGPU: Add VI i16 support"Tom Stellard2016-11-041-32/+0
| | | | | | This reverts commit r285939 and r285948. These broke some conformance tests. llvm-svn: 285995
* AMDGPU: Add VI i16 supportTom Stellard2016-11-031-0/+32
| | | | | | | | Patch By: Wei Ding Differential Revision: https://reviews.llvm.org/D18049 llvm-svn: 285939
* [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin2016-09-231-15/+15
| | | | | | Differential revision: https://reviews.llvm.org/D24738 llvm-svn: 282234
* [AMDGPU] Refactor VOP3 instruction TD definitionsValery Pykhtin2016-09-201-0/+404
Differential revision: https://reviews.llvm.org/D24664 llvm-svn: 281965
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