Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | AMDGPU: Add MachineInstr overloads for instruction format tests | Matt Arsenault | 2015-10-20 | 1 | -2/+1 |
| | | | | llvm-svn: 250797 | ||||
* | AMDGPU: Simplify debug printing | Matt Arsenault | 2015-09-10 | 1 | -1/+1 |
| | | | | llvm-svn: 247345 | ||||
* | AMDGPU/SI: Remove VCCReg | Matt Arsenault | 2015-08-08 | 1 | -2/+11 |
| | | | | llvm-svn: 244380 | ||||
* | AMDGPU/SI: Remove source uses of VCCReg | Matt Arsenault | 2015-08-08 | 1 | -11/+32 |
| | | | | llvm-svn: 244379 | ||||
* | AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions | Tom Stellard | 2015-07-14 | 1 | -6/+27 |
| | | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11061 llvm-svn: 242146 | ||||
* | AMDGPU/SI: Select mad patterns to v_mac_f32 | Tom Stellard | 2015-07-13 | 1 | -2/+14 |
| | | | | | | | | | The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038 | ||||
* | AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with ↵ | Tom Stellard | 2015-07-09 | 1 | -1/+1 |
| | | | | | | | | | one use This is convered by existing testcases and will be exposed by a future commit. llvm-svn: 241817 | ||||
* | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -0/+272 |
llvm-svn: 239657 |