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path: root/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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* AMDGPU: Detect kernarg segment pointerMatt Arsenault2017-07-141-1/+4
* AMDGPU: Setup SP/FP in callee function prolog/epilogMatt Arsenault2017-06-261-0/+1
* AMDGPU: Partially fix implicit.buffer.ptr intrinsic handlingMatt Arsenault2017-06-261-5/+5
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-7/+12
* AMDGPU: GFX9 GS and HS shaders always have the scratch wave offset in SGPR5Marek Olsak2017-05-041-1/+7
* AMDGPU: Add StackPtr and FramePtr registers to MFIMatt Arsenault2017-04-241-0/+2
* AMDGPU: Refactor SIMachineFunctionInfo slightlyMatt Arsenault2017-04-111-15/+25
* AMDGPU: Refactor argument loweringMatt Arsenault2017-04-111-1/+1
* AMDGPU: Don't use stack space for SGPR->VGPR spillsMatt Arsenault2017-02-211-42/+51
* AMDGPU add support for spilling to a user sgpr pointed buffersTom Stellard2017-01-251-2/+13
* AMDGPU/SI: Make a function constTom Stellard2016-12-201-1/+0
* AMDGPU/SI: Add a MachineMemOperand to MIMG instructionsTom Stellard2016-12-201-0/+1
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-161-1/+1
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-14/+4
* AMDGPU: Remove unused tracking of flat instructionsMatt Arsenault2016-08-111-1/+0
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-4/+4
* AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard2016-07-281-1/+2
* AMDGPU: Make AMDGPUMachineFunction fields privateMatt Arsenault2016-07-261-3/+0
* AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault2016-07-221-1/+11
* AMDGPU/SI: Emit the number of SGPR and VGPR spillsMarek Olsak2016-07-131-0/+2
* SIMachineFunctionInfo.cpp: Appease msc18 to use std::array.NAKAMURA Takumi2016-06-271-2/+2
* Reformat.NAKAMURA Takumi2016-06-271-1/+1
* Reformat blank lines.NAKAMURA Takumi2016-06-271-2/+0
* [AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in t...Konstantin Zhuravlyov2016-06-251-4/+6
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-5/+6
* AMDGPU: Add option to disable spilling SGPRs to VGPRs.Matt Arsenault2016-06-231-2/+9
* [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegsKonstantin Zhuravlyov2016-05-241-3/+3
* [AMDGPU] Move reserved vgpr count for trap handler usage to SIMachineFunction...Konstantin Zhuravlyov2016-04-261-0/+4
* AMDGPU: Add queue ptr intrinsicMatt Arsenault2016-04-251-0/+3
* AMDGPU: allow specifying a workgroup size that needs to fit in a compute unitTom Stellard2016-04-141-6/+7
* AMDGPU/SI: Use the correct scratch wave offset register for shaders.Tom Stellard2016-04-141-3/+6
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-3/+5
* AMDGPU/SI: Add support for spiling SGPRs to scratch bufferTom Stellard2016-03-041-10/+5
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-4/+20
* AMDGPU/SI: Add s_waitcnt at the end of non-void functionsMarek Olsak2016-01-131-0/+1
* AMDGPU/SI: Add new target attribute InitialPSInputAddrMarek Olsak2016-01-131-1/+4
* AMDGPU: Avoid assertions after SGPR spilling failedNicolai Haehnle2016-01-041-0/+11
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-9/+71
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-301-0/+8
* AMDGPU: Check feature attributes in SIMachineFunctionInfoMatt Arsenault2015-11-251-3/+36
* AMDGPU: Also track whether SGPRs were spilledMatt Arsenault2015-11-051-0/+1
* MachineRegisterInfo: Remove UsedPhysReg infrastructureMatthias Braun2015-07-141-1/+0
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+77
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-18/+0
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+18
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