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* AMDGPU: Improve accuracy of instruction rates for some FP instructionsMatt Arsenault2015-08-221-7/+22
| | | | llvm-svn: 245774
* AMDGPU: Move CI instructions into CIInstructions.tdMatt Arsenault2015-08-221-70/+0
| | | | | | There are still a couple of CI patterns left in SIInstructions. llvm-svn: 245767
* AMDGPU/SI: Remove source uses of VCCRegMatt Arsenault2015-08-081-2/+4
| | | | llvm-svn: 244379
* AMDGPU/SI: v_mac_legacy_f32 does not exist on VITom Stellard2015-08-071-6/+6
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11810 llvm-svn: 244322
* AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CITom Stellard2015-08-061-9/+25
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11604 llvm-svn: 244254
* AMDGPU/SI: Use ComplexPatterns for SMRD addressing modesTom Stellard2015-08-061-54/+11
| | | | | | | | | | | | Summary: This allows us to consolidate several of the TableGen patterns. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11602 llvm-svn: 244253
* AMDGPU/SI: Remove EXECRegMatt Arsenault2015-08-051-4/+4
| | | | | | For the same reasons as the other physical registers. llvm-svn: 244062
* AMDGPU: Remove SCCReg.Matt Arsenault2015-08-051-4/+4
| | | | | | | These should be handled as a physical register rather than a virtual register class with one member. llvm-svn: 244061
* AMDGPU/SI: Remove unused pattern for f32 constant loadsTom Stellard2015-07-311-1/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11603 llvm-svn: 243719
* AMDGPU: don't match vgpr loads for constant loadsMarek Olsak2015-07-271-3/+0
| | | | | | | | | | | | Author: Dave Airlie <airlied@redhat.com> In order to implement indirect sampler loads, we don't want to match on a VGPR load but an SGPR one for constants, as we cannot feed VGPRs to the sampler only SGPRs. this should be applicable for llvm 3.7 as well. llvm-svn: 243294
* AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaroundMarek Olsak2015-07-271-2/+2
| | | | | | This is a candidate for 3.7. llvm-svn: 243263
* AMDGPU: Set isMoveImm on s_movk_i32Matt Arsenault2015-07-211-1/+1
| | | | llvm-svn: 242747
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-131-1/+13
| | | | | | | | | The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+3327
| | | | llvm-svn: 239657
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-965/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+965
llvm-svn: 160270
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