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path: root/llvm/lib/Target/AMDGPU/SIFrameLowering.h
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* AMDGPU: Setup SP/FP in callee function prolog/epilogMatt Arsenault2017-06-261-0/+4
| | | | llvm-svn: 306312
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-0/+2
| | | | | | | | Partially implement callee-side for arguments and return values. byval doesn't work properly, and most likely sret or other on-stack return values most as well. llvm-svn: 303308
* AMDGPU: Shift down reserved SP register like scratch wave offsetMatt Arsenault2017-04-251-1/+1
| | | | llvm-svn: 301367
* [AMDGPU] Split R600/SI getFrameIndexReference and emit stack object offsets ↵Konstantin Zhuravlyov2017-03-101-0/+2
| | | | | | | | for SI Differential Revision: https://reviews.llvm.org/D29674 llvm-svn: 297499
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-2/+1
| | | | llvm-svn: 295554
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What ↵Eugene Zelenko2016-12-091-3/+4
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 289282
* AMDGPU: Refactor frame loweringMatt Arsenault2016-08-311-0/+23
| | | | | | This will make future changes easier. llvm-svn: 280296
* [AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in ↵Konstantin Zhuravlyov2016-06-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | the kernel code header Debugger prologue is emitted if -mattr=+amdgpu-debugger-emit-prologue. Debugger prologue writes work group IDs and work item IDs to scratch memory at fixed location in the following format: - offset 0: work group ID x - offset 4: work group ID y - offset 8: work group ID z - offset 16: work item ID x - offset 20: work item ID y - offset 24: work item ID z Set - amd_kernel_code_t::debug_wavefront_private_segment_offset_sgpr to scratch wave offset reg - amd_kernel_code_t::debug_private_segment_buffer_sgpr to scratch rsrc reg - amd_kernel_code_t::is_debug_supported to true if all debugger features are enabled Differential Revision: http://reviews.llvm.org/D20335 llvm-svn: 273769
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-0/+2
| | | | | | | | | Split AMDGPUSubtarget into amdgcn/r600 specific subclasses. This removes most of the static_casting of the basic codegen classes everywhere, and tries to restrict the features visible on the wrong target. llvm-svn: 273652
* AMDGPU: Remove SIPrepareScratchRegsMatt Arsenault2015-11-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | It does not work because of emergency stack slots. This pass was supposed to eliminate dummy registers for the spill instructions, but the register scavenger can introduce more during PrologEpilogInserter, so some would end up left behind if they were needed. The potential for spilling the scratch resource descriptor and offset register makes doing something like this overly complicated. Reserve registers to use for the resource descriptor and use them directly in eliminateFrameIndex. Also removes creating another scratch resource descriptor when directly selecting scratch MUBUF instructions. The choice of which registers are reserved is temporary. For now it attempts to pick the next available registers after the user and system SGPRs. llvm-svn: 254329
* AMDGPU: Create emergency stack slots during frame loweringMatt Arsenault2015-11-061-0/+31
Test has a bogus verifier error which will be fixed by later commits. llvm-svn: 252327
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