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* AMDGPU: Match load d16 hi instructionsMatt Arsenault2017-09-201-10/+37
| | | | | | | | | | | | Also starts selecting global loads for constant address in some cases. Some end up selecting to mubuf still, which requires investigation. We still get sub-optimal regalloc and extra waitcnts inserted due to not really tracking the liveness of the separate register halves. llvm-svn: 313716
* AMDGPU: Cleanup load/store PatFragsMatt Arsenault2017-09-201-19/+19
| | | | | | Try to use a consistent naming scheme. llvm-svn: 313713
* AMDGPU: Match store d16_hi instructionsMatt Arsenault2017-09-201-0/+5
| | | | llvm-svn: 313712
* AMDGPU: Add ds_{read|write}_addtid_b32 definitionsMatt Arsenault2017-09-011-0/+10
| | | | llvm-svn: 312349
* AMDGPU: Add most d16 load/store instruction definitionsMatt Arsenault2017-09-011-0/+25
| | | | | | | Doesn't include the tied operand necessary for the loads, but is enough for the assembler to work. llvm-svn: 312347
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-311-3/+3
| | | | | | | | | | See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33542 llvm-svn: 304309
* Revert earlier change. ds permute operations affect lgkm counter. Kannan Narayanan2017-04-191-2/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D32254 llvm-svn: 300791
* [AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two.Dmitry Preobrazhensky2017-04-141-14/+2
| | | | | | | | | | Fixed bug 32551: https://bugs.llvm.org//show_bug.cgi?id=32551 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31809 llvm-svn: 300319
* [AMDGPU][MC] Corrected ds_wrxchg2* to support two offsetsDmitry Preobrazhensky2017-04-121-7/+21
| | | | | | | | | | Fixed bug 28227: https://bugs.llvm.org//show_bug.cgi?id=28227 Reviewers: vpykhtin Differential Revision: https://reviews.llvm.org/D31808 llvm-svn: 300066
* [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing.Kannan Narayanan2017-04-121-0/+2
| | | | | | Based on comments in https://reviews.llvm.org/D31161. llvm-svn: 300023
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-071-35/+47
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* AMDGPU: Add ds_nop to assemblerMatt Arsenault2017-02-281-1/+21
| | | | llvm-svn: 296513
* AMDGPU: Add definitions for ds_{read|write}_b{96|128}Matt Arsenault2017-02-281-4/+19
| | | | | | | | | It's not clear to me if this is always better than doing ds_write2_b64 This adds the constraint of a 128-bit register input instead of a pair of 64-bit. llvm-svn: 296512
* [AMDGPU][mc] Fix AddressSanitizer leftover issue in gfx7_asm_all testArtem Tamazov2017-02-031-0/+1
| | | | | | Issue occurs when assembling "ds_ordered_count v0, v0 gds". llvm-svn: 294004
* AMDGPU: Add VI i16 supportTom Stellard2016-11-101-2/+8
| | | | | | | | Patch By: Wei Ding Differential Revision: https://reviews.llvm.org/D18049 llvm-svn: 286464
* Revert "AMDGPU: Add VI i16 support"Tom Stellard2016-11-041-8/+2
| | | | | | This reverts commit r285939 and r285948. These broke some conformance tests. llvm-svn: 285995
* AMDGPU: Add VI i16 supportTom Stellard2016-11-031-2/+8
| | | | | | | | Patch By: Wei Ding Differential Revision: https://reviews.llvm.org/D18049 llvm-svn: 285939
* AMDGPU: Whitespace fixesMatt Arsenault2016-11-011-7/+7
| | | | llvm-svn: 285659
* [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.Artem Tamazov2016-10-211-4/+4
| | | | | | | | Fixes Bug 28215. Lit tests updated. Differential Revision: https://reviews.llvm.org/D25837 llvm-svn: 284825
* AMDGPU: Partially fix reported code size for some instructionsMatt Arsenault2016-10-061-0/+1
| | | | | | | | These ones need to have the size on the pseudo instruction set for getInstSizeInBytes to work correctly. These also have a statically known size. llvm-svn: 283437
* [AMDGPU][mc] Add support for ds_add_[rtn_]f32.Artem Tamazov2016-09-211-0/+5
| | | | | | | | | Lit tests added. Resolves https://github.com/RadeonOpenCompute/hcc/issues/122. Differential Revision: https://reviews.llvm.org/D24765 llvm-svn: 282086
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-011-0/+894
Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
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