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path: root/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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* [AMDGPU][MC] Fix for sanitizer failure in 364645Dmitry Preobrazhensky2019-06-281-4/+10
* [AMDGPU][MC] Enabled constant expressions as operands of sendmsgDmitry Preobrazhensky2019-06-281-169/+87
* AMDGPU/MC: Add .amdgpu_lds directiveNicolai Haehnle2019-06-251-0/+58
* [AMDGPU] gfx1010 wave32 metadataStanislav Mekhanoshin2019-06-171-0/+32
* [AMDGPU] gfx1010 base changes for wave32Stanislav Mekhanoshin2019-06-131-11/+47
* [AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setregDmitry Preobrazhensky2019-06-131-94/+69
* [AMDGPU] gfx1010 dpp16 and dpp8Stanislav Mekhanoshin2019-06-121-15/+130
* [AMDGPU] gfx1010 premlane instructionsStanislav Mekhanoshin2019-06-121-0/+19
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-111-1/+1
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-101-1/+1
* [AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operandsDmitry Preobrazhensky2019-06-031-4/+16
* [AMDGPU][MC] Enabled constant expressions as operands of s_waitcntDmitry Preobrazhensky2019-05-271-36/+28
* [AMDGPU][MC] Corrected parsing of op_sel* and neg_* modifiersDmitry Preobrazhensky2019-05-221-34/+32
* [AMDGPU][MC] Corrected parsing of NAME:VALUE modifiersDmitry Preobrazhensky2019-05-171-33/+17
* [AMDGPU][MC] Enabled expressions for most operands which accept integer valuesDmitry Preobrazhensky2019-05-171-64/+103
* [AMDGPU] Create a TargetInfo header. NFCRichard Trieu2019-05-141-0/+1
* [AMDGPU] gfx1010 exp modificationsStanislav Mekhanoshin2019-05-081-1/+6
* [AMDGPU] gfx1010 allows VOP3 to have a literalStanislav Mekhanoshin2019-05-021-10/+64
* [AMDGPU] gfx1010 constant bus limitStanislav Mekhanoshin2019-05-021-2/+32
* [AMDGPU] gfx1010 MIMG implementationStanislav Mekhanoshin2019-05-011-7/+206
* [AMDGPU] gfx1010 DS implementationStanislav Mekhanoshin2019-05-011-2/+3
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-6/+42
* Move if() to newline to stop ambiguity over whether it should be else if. NFCI.Simon Pilgrim2019-04-291-1/+2
* [AMDGPU] gfx1010 VOPC implementationStanislav Mekhanoshin2019-04-261-1/+2
* [AMDGPU] gfx1010 VOP3 and VOP3P implementationStanislav Mekhanoshin2019-04-261-0/+9
* [AMDGPU] gfx1010 VOP2 changesStanislav Mekhanoshin2019-04-261-22/+78
* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-241-19/+52
* [AMDGPU] Add gfx1010 target definitionsStanislav Mekhanoshin2019-04-241-2/+6
* [AMDGPU][MC] Parser cleanup and refactoringDmitry Preobrazhensky2019-04-241-93/+48
* [AMDGPU][MC] Corrected parsing of SP3 'neg' modifierDmitry Preobrazhensky2019-04-221-24/+58
* [AMDGPU][MC] Corrected handling of "-" before expressionsDmitry Preobrazhensky2019-04-171-38/+58
* [AMDGPU][MC] Corrected parsing of registersDmitry Preobrazhensky2019-04-171-27/+126
* AMDGPU: Fix names for generation featuresMatt Arsenault2019-04-031-1/+1
* [AMDGPU][MC] Corrected conversion rules for inlinable constants to match rule...Dmitry Preobrazhensky2019-03-291-15/+15
* [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodesDmitry Preobrazhensky2019-03-291-7/+7
* Revert of 357063 [AMDGPU][MC] Corrected handling of tied src for atomic retur...Dmitry Preobrazhensky2019-03-271-7/+7
* [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodesDmitry Preobrazhensky2019-03-271-7/+7
* AMDHSA: Fix COMPUTE_PGM_RSRC2.USER_SGPR calculation when parsing ISA assemblyKonstantin Zhuravlyov2019-03-201-7/+7
* [AMDGPU] Added MsgPack format PAL metadataTim Renouf2019-03-201-13/+50
* [AMDGPU] Factored PAL metadata handling out into its own classTim Renouf2019-03-201-4/+12
* [AMDGPU][MC] Corrected checks for DS offset0 rangeDmitry Preobrazhensky2019-03-201-1/+1
* [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, priva...Dmitry Preobrazhensky2019-03-201-0/+41
* [AMDGPU] Silence gcc 7 warningsStanislav Mekhanoshin2019-03-131-3/+3
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-121-0/+37
* Use bitset for assembler predicatesStanislav Mekhanoshin2019-03-111-2/+3
* [AMDGPU] Mark enum types in SIDefines.h as unsignedStanislav Mekhanoshin2019-03-111-2/+2
* [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b3...Dmitry Preobrazhensky2019-03-041-44/+73
* [AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operandsDmitry Preobrazhensky2019-02-271-11/+15
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instruc...Dmitry Preobrazhensky2019-02-271-4/+87
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-081-0/+88
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