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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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* Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle2020-02-031-2/+0
* [AMDGPU] Invert the handling of skip insertion.cdevadas2020-01-151-0/+2
* CMake: Make most target symbols hidden by defaultTom Stellard2020-01-141-1/+1
* [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.Michael Liao2020-01-141-1/+1
* Sink all InitializePasses.h includesReid Kleckner2019-11-131-0/+1
* AMDGPU: Add default denormal mode to MachineFunctionInfoMatt Arsenault2019-11-011-0/+2
* Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs."Jay Foad2019-10-101-3/+0
* AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault2019-10-101-2/+2
* AMDGPU: Run AMDGPUCodeGenPrepare after scalar optsMatt Arsenault2019-08-271-6/+5
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-5/+5
* [AMDGPU] Printf runtime binding passStanislav Mekhanoshin2019-08-121-0/+4
* [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs.Michael Liao2019-07-251-0/+3
* [AMDGPU] Add the adjusted FP as a livein register.Michael Liao2019-07-161-25/+27
* AMDGPU: Serialize mode from MachineFunctionInfoMatt Arsenault2019-07-101-0/+3
* AMDGPU: Make AMDGPUPerfHintAnalysis an SCC passMatt Arsenault2019-07-051-0/+2
* AMDGPU: Add pass to lower SGPR spillsMatt Arsenault2019-07-031-0/+4
* [AMDGPU] Enable serializing of argument info.Michael Liao2019-07-031-0/+79
* [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent...Alexander Timofeev2019-07-021-0/+1
* Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault2019-06-191-1/+2
* [AMDGPU] Propagate function attributes thru bitcastsStanislav Mekhanoshin2019-06-171-3/+4
* [AMDGPU] gfx1010 wavefrontsize intrinsic foldingStanislav Mekhanoshin2019-06-171-1/+1
* [AMDGPU] Pass to propagate ABI attributes from kernels to the functionsStanislav Mekhanoshin2019-06-171-4/+11
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-111-1/+1
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-101-1/+1
* [AMDGPU] Create a TargetInfo header. NFCRichard Trieu2019-05-141-0/+1
* [AMDGPU] gfx1010 GCNRegBankReassign passStanislav Mekhanoshin2019-05-011-0/+2
* [AMDGPU] gfx1010 GCNNSAReassign passStanislav Mekhanoshin2019-05-011-0/+15
* [GlobalISel] Introduce a CSEConfigBase class to allow targets to define their...Amara Emerson2019-04-151-0/+6
* Reapply [ValueTracking] Support min/max selects in computeConstantRange()Nikita Popov2019-04-071-2/+9
* [AMDGPU] Add MachineDCE pass after RenameIndependentSubregsStanislav Mekhanoshin2019-04-051-0/+9
* [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning2019-04-011-7/+5
* AMDGPU: Add additional MIR tests for exec mask optimizationsMatt Arsenault2019-03-271-3/+11
* CodeGen: Refactor regallocator command line and target selectionMatt Arsenault2019-03-191-6/+6
* [AMDGPU] Add an experimental buffer fat pointer address space.Neil Henning2019-03-181-2/+3
* AMDGPU: Partially fix default device for HSAMatt Arsenault2019-03-171-1/+2
* MIR: Allow targets to serialize MachineFunctionInfoMatt Arsenault2019-03-141-0/+73
* AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV)Aakanksha Patil2019-03-071-1/+3
* AMDGPU: Fix typoMatt Arsenault2019-02-281-1/+1
* AMDGPU: Enable function calls by defaultMatt Arsenault2019-02-281-4/+9
* AMDGPU: Remove debugger related subtarget featuresMatt Arsenault2019-02-211-2/+0
* [AMDGPU] Enable DPP combiner pass by default.Valery Pykhtin2019-02-111-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd tryDavid Stuttard2019-01-141-0/+1
* Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-131-3/+1
* [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil2018-12-121-1/+3
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-0/+9
* [Targets] Add errors for tiny and kernel codemodel on targets that don't supp...David Green2018-12-071-7/+1
* [AMDGPU] Partial revert of rL348371: Turn on the DPP combiner by defaultValery Pykhtin2018-12-061-1/+1
* [AMDGPU]: Turn on the DPP combiner by defaultValery Pykhtin2018-12-051-1/+1
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-0/+8
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