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* AMDGPU: Implement readcyclecounterMatt Arsenault2016-02-271-0/+1
| | | | | | | | | | This matches the behavior of the HSAIL clock instruction. s_realmemtime is used if the subtarget supports it, and falls back to s_memtime if not. Also introduces new intrinsics for each of s_memtime / s_memrealtime. llvm-svn: 262119
* AMDGPU: Set element_size in private resource descriptorMatt Arsenault2016-02-121-0/+5
| | | | | | | | | Introduce a subtarget feature for this, and leave the default with the current behavior which assumes up to 16-byte loads/stores can be used. The field also seems to have the ability to be set to 2 bytes, but I'm not sure what that would be used for. llvm-svn: 260651
* AMDGPU: Match some med3 patternsMatt Arsenault2016-01-281-0/+5
| | | | llvm-svn: 259089
* AMDGPU: Fix default device handlingMatt Arsenault2016-01-271-5/+0
| | | | | | | | | | | | | | | | | | | When no device name is specified, default to kaveri for HSA since SI is not supported and it woud fail. Default to "tahiti" instead of "SI" since these are effectively the same, and tahiti is an actual device. Move default device handling to the TargetMachine rather than the AMDGPUSubtarget. The module ISA version is computed from the device name provided with the target machine, so the attributes printed by the AsmPrinter were inconsistent with those computed in the subtarget. Also remove DevName field from subtarget since it's redundant with getCPU() in the superclass. llvm-svn: 258901
* AMDGPU: Remove Feature64BitPtrMatt Arsenault2016-01-231-5/+0
| | | | | | | This is a leftover from AMDIL that doesn't do anything and doesn't belong here. llvm-svn: 258606
* AMDGPU/SI: Pass whether to use the SI scheduler via Target AttributeTom Stellard2016-01-211-0/+5
| | | | | | | | | | | | | | | | Summary: Currently the SI scheduler can be selected via command line option, but it turned out it would be better if it was selectable via a Target Attribute. This patch adds "si-scheduler" attribute to the backend. Reviewers: tstellarAMD, echristo Subscribers: echristo, arsenm Differential Revision: http://reviews.llvm.org/D16192 llvm-svn: 258386
* AMDGPU: Add subtarget feature for instruction ratesMatt Arsenault2016-01-181-0/+5
| | | | llvm-svn: 258085
* AMDGPU/SI: Update ISA version for FIJIChangpeng Fang2016-01-131-1/+2
| | | | llvm-svn: 257666
* AMDGPU: add +xnack featureNicolai Haehnle2016-01-041-0/+5
| | | | | | | | | | | | | | | | | | | Summary: Enabling this feature will account for the two SGPRs used by the hardware to store the XNACK_MASK physically. The hardware only requires this reservation when the XNACK feature is explicitly enabled. At some point, HSA will probably want to do that, but it does increase SGPR register pressure, so leave it disabled by default for now (but do add a small test). Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15869 llvm-svn: 256794
* AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang2015-12-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. NOTE: re-commit by fixing a failure in Codegen/AMDGPU/llvm.dbg.value.ll Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256282
* Revert "AMDGPU/SI: Use flat for global load/store when targeting HSA"Rafael Espindola2015-12-221-5/+0
| | | | | | | | This reverts commit r256273. It broke CodeGen/AMDGPU/llvm.dbg.value.ll llvm-svn: 256275
* AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang2015-12-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256273
* AMDGPU: Error if too many user SGPRs usedMatt Arsenault2015-11-301-0/+3
| | | | llvm-svn: 254332
* AMDGPU: Cleanup includesMatt Arsenault2015-11-061-6/+3
| | | | llvm-svn: 252328
* AMDGPU: Create emergency stack slots during frame loweringMatt Arsenault2015-11-061-6/+7
| | | | | | Test has a bogus verifier error which will be fixed by later commits. llvm-svn: 252327
* AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsetsTom Stellard2015-07-161-0/+5
| | | | | | | | | | | | | | Summary: We can safely assume that the high bit of scratch offsets will never be set, because this would require at least 128 GB of GPU memory. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11225 llvm-svn: 242433
* AMDGPU/SI: Add debugging subtarget feature for DS offsetsMatt Arsenault2015-07-061-0/+5
| | | | | | | | We don't have a good way to detect most situations where DS offsets are usable on SI, so add an option to force using them even if unsafe for debugging performance problems. llvm-svn: 241462
* AMDGPU/SI: Add hsa code object directivesTom Stellard2015-06-261-0/+13
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10757 llvm-svn: 240831
* AMDGPU/SI: There are no implicit kernel args in the amdhsa ABITom Stellard2015-06-261-0/+7
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10706 llvm-svn: 240830
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+282
| | | | llvm-svn: 239657
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-161-36/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-161-0/+36
llvm-svn: 160270
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