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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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* AMDGPU: Move R600 specific code out of AMDGPUISelLowering.cppTom Stellard2016-05-021-39/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: jvesely, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19736 llvm-svn: 268267
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-281-8/+2
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-261-20/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D17176 llvm-svn: 267606
* AMDGPU: Add DAG to debug dumpMatt Arsenault2016-04-251-2/+2
| | | | | | Also reorder case to match enum order llvm-svn: 267449
* AMDGPU: Re-visit nodes in performAndCombineMatt Arsenault2016-04-221-0/+5
| | | | | | This fixes test regressions when i64 loads/stores are made promote. llvm-svn: 267240
* AMDGPU: Remove custom load/store scalarizationMatt Arsenault2016-04-141-78/+4
| | | | llvm-svn: 266385
* AMDGPU: Fold bitcasts of scalar constants to vectorsMatt Arsenault2016-04-141-0/+34
| | | | | | | This cleans up some messes since the individual scalar components can be CSEed. llvm-svn: 266376
* AMDGPU: Add atomic_inc + atomic_dec intrinsicsMatt Arsenault2016-04-121-0/+2
| | | | | | | These are different than atomicrmw add 1 because they have an additional input value to clamp the result. llvm-svn: 266074
* AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2}Tom Stellard2016-04-011-0/+1
| | | | | | | | | | | | | | | | | Summary: Implement BUFFER_ATOMIC_CMPSWAP{,_X2} instructions on all GCN targets, and FLAT_ATOMIC_CMPSWAP{,_X2} on CI+. 32-bit instruction variants tested manually on Kabini and Bonaire. Tests and parts of code provided by Jan Veselý. Patch by: Vedran Miletić Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: jvesely, scchan, kanarayan, arsenm Differential Revision: http://reviews.llvm.org/D17280 llvm-svn: 265170
* Silencing warnings from MSVC 2015 Update 2. All of these changes silence ↵Aaron Ballman2016-03-301-1/+1
| | | | | | "C4334 '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)". NFC. llvm-svn: 264929
* AMDGPU: R600 code splitting cleanupMatt Arsenault2016-03-111-14/+0
| | | | | | | Move a few functions only used by R600 to R600 specific code, fix header macros to stop using R600, mark classes as final. llvm-svn: 263204
* AMDGPU: Move function only used by R600Matt Arsenault2016-03-071-17/+0
| | | | llvm-svn: 262853
* AMDGPU: Simplify boolean conditional return statementsMatt Arsenault2016-03-021-4/+1
| | | | | | Patch by Richard Thomson llvm-svn: 262536
* AMDGPU: Don't emit build_pair during udivrem legalizationMatt Arsenault2016-03-011-6/+11
| | | | | | | | Technically you aren't supposed to emit these after type legalization for some reason, and we use vector extracts of bitcasted integers as the canonical way to do this. llvm-svn: 262298
* AMDGPU: Set HasExtractBitInsnMatt Arsenault2016-03-011-0/+11
| | | | | | | | | | This currently does not have the control over the bitwidth, and there are missing optimizations to reduce the integer to 32-bit if it can be. But in most situations we do want the sinking to occur. llvm-svn: 262296
* AMDGPU: Rename intrinsic to better match instruction nameMatt Arsenault2016-02-131-1/+1
| | | | | | Also fixes missing f32 test. llvm-svn: 260780
* AMDGPU: Fix mishandling alignment when scalarizing vector loads/storesMatt Arsenault2016-02-121-2/+5
| | | | | | | I don't think this was causing any real problems, so I'm not sure how to test for this. llvm-svn: 260646
* AMDGPU: Split R600 and SI store loweringMatt Arsenault2016-02-111-63/+2
| | | | | | | These were only sharing some somewhat incorrect logic for when to scalarize or split vectors. llvm-svn: 260490
* AMDGPU: Split R600 and SI load loweringMatt Arsenault2016-02-101-93/+0
| | | | | | | These weren't actually sharing anything in the common LowerLOAD. llvm-svn: 260398
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-091-5/+2
| | | | llvm-svn: 260316
* AMDGPU: Remove bfi and bfm intrinsicsMatt Arsenault2016-02-081-11/+0
| | | | | | Nothing is using them. llvm-svn: 260123
* AMDGPU: Account for LDS alignmentMatt Arsenault2016-02-051-4/+9
| | | | | | | | | | | | | The current situation isn't great, because the amount of padding requires is determined by the inverse order of the first encountered use. We should eventually somehow sort these to minimize wasted space. Another problem is the alignment of kernel arguments isn't respected. The group_segment_alignment is always emitted as the default 16, and typed arguments with higher alignments or an explicitly set alignment are also ignored. llvm-svn: 259912
* Refactor backend diagnostics for unsupported featuresOliver Stannard2016-02-021-5/+7
| | | | | | | | | | | | | | | | | Re-commit of r258951 after fixing layering violation. The BPF and WebAssembly backends had identical code for emitting errors for unsupported features, and AMDGPU had very similar code. This merges them all into one DiagnosticInfo subclass, that can be used by any backend. There should be minimal functional changes here, but some AMDGPU tests have been updated for the new format of errors (it used a slightly different format to BPF and WebAssembly). The AMDGPU error messages will now benefit from having precise source locations when debug info is available. llvm-svn: 259498
* AMDGPU: Remove 24-bit intrinsicsMatt Arsenault2016-01-291-16/+0
| | | | | | | The known bit matching code seems to work reasonably well, so these shouldn't really be needed. llvm-svn: 259180
* AMDGPU: Match fmed3 patterns with legacy fmin/fmaxMatt Arsenault2016-01-281-2/+7
| | | | llvm-svn: 259090
* AMDGPU: Match some med3 patternsMatt Arsenault2016-01-281-1/+4
| | | | llvm-svn: 259089
* Revert r259035, it introduces a cyclic library dependencyOliver Stannard2016-01-281-5/+5
| | | | llvm-svn: 259045
* Add backend dignostic printer for unsupported featuresOliver Stannard2016-01-281-5/+5
| | | | | | | | | | | | | | | | Re-commit of r258951 after fixing layering violation. The related LLVM patch adds a backend diagnostic type for reporting unsupported features, this adds a printer for them to clang. In the case where debug location information is not available, I've changed the printer to report the location as the first line of the function, rather than the closing brace, as the latter does not give the user any information. This also affects optimisation remarks. Differential Revision: http://reviews.llvm.org/D16590 llvm-svn: 259035
* Revert r258951 (and r258950), "Refactor backend diagnostics for unsupported ↵NAKAMURA Takumi2016-01-281-6/+5
| | | | | | | | | | | features" It broke layering violation in LLVMIR. clang r258950 "Add backend dignostic printer for unsupported features" llvm r258951 "Refactor backend diagnostics for unsupported features" llvm-svn: 259016
* Refactor backend diagnostics for unsupported featuresOliver Stannard2016-01-271-5/+6
| | | | | | | | | | | | | | | | | | | | | The BPF and WebAssembly backends had identical code for emitting errors for unsupported features, and AMDGPU had very similar code. This merges them all into one DiagnosticInfo subclass, that can be used by any backend. There should be minimal functional changes here, but some AMDGPU tests have been updated for the new format of errors (it used a slightly different format to BPF and WebAssembly). The AMDGPU error messages will now benefit from having precise source locations when debug info is available. The implementation of DiagnosticInfoUnsupported::print must be in lib/Codegen rather than in the existing file in lib/IR/ to avoid introducing a dependency from IR to CodeGen. Differential Revision: http://reviews.llvm.org/D16590 llvm-svn: 258951
* AMDGPU: Restore AMDGPU prefixed rsq intrinsic for nowMatt Arsenault2016-01-261-4/+0
| | | | | | Also move into backend intrinsics to discourage use of the old name. llvm-svn: 258783
* AMDGPU: Remove more unused intrinsicsMatt Arsenault2016-01-231-23/+0
| | | | | | Replace tests with lrp with basic IR expansion llvm-svn: 258612
* AMDGPU: Move amdgcn intrinsic handling into SITargetLoweringMatt Arsenault2016-01-231-72/+2
| | | | llvm-svn: 258608
* AMDGPU: Rename intrinsics to use amdgcn prefixMatt Arsenault2016-01-221-8/+10
| | | | | | | | | | | The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
* AMDGPU: Remove AMDGPU.trunc intrinsicMatt Arsenault2016-01-201-2/+0
| | | | llvm-svn: 258348
* AMDGPU: Remove AMDIL.round.nearest intrinsicMatt Arsenault2016-01-201-2/+0
| | | | llvm-svn: 258346
* AMDGPU: Remove abs intrinsicMatt Arsenault2016-01-201-14/+0
| | | | llvm-svn: 258343
* AMDGPU: Remove min/max intrinsicsMatt Arsenault2016-01-201-44/+0
| | | | | | This removes support for mesa 11.0.x llvm-svn: 258342
* AMDGPU: Reduce 64-bit SRAsMatt Arsenault2016-01-181-0/+60
| | | | llvm-svn: 258096
* AMDGPU: Split 64-bit and of constant upMatt Arsenault2016-01-181-1/+60
| | | | | | | | | | This breaks the tests that were meant for testing 64-bit inline immediates, so move those to shl where they won't be broken up. This should be repeated for the other related bit ops. llvm-svn: 258095
* AMDGPU: Generalize shl combineMatt Arsenault2016-01-181-8/+14
| | | | | | | Reduce 64-bit shl with constant > 32. We already special cased this for the == 32 case, but this also works for any >= 32 constant. llvm-svn: 258092
* AMDGPU: Reduce 64-bit lshr by constant to 32-bitMatt Arsenault2016-01-181-0/+44
| | | | | | 64-bit shifts are very slow on some subtargets. llvm-svn: 258090
* GlobalValue: use getValueType() instead of getType()->getPointerElementType().Manuel Jacob2016-01-161-2/+2
| | | | | | | | | | | | Reviewers: mjacob Subscribers: jholewinski, arsenm, dsanders, dblaikie Patch by Eduard Burtescu. Differential Revision: http://reviews.llvm.org/D16260 llvm-svn: 257999
* AMDGPU/SI: Add support for non-void functionsMarek Olsak2016-01-131-0/+6
| | | | | | | | | | | | | | | | | | | Summary: Return values can be stored in SGPRs (i32) and VGPRs (f32). This will be used by functions which expect some bytecode or other binary to be appended at the end. It allows defining in which registers the return values will be stored. v2: don't do this for compute shaders Reviewers: tstellarAMD, arsenm Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D16033 llvm-svn: 257621
* AMDGPU: Implement {{s|u}}int_to_fp i64 -> f32Matt Arsenault2016-01-111-19/+98
| | | | | | | The old lowering for uint_to_fp failed opencl conformance. It might be OK for fast math mode, but I'm not sure. llvm-svn: 257393
* AMDGPU: Fix ctlz combine for sub 32-bit typesMatt Arsenault2016-01-111-6/+24
| | | | llvm-svn: 257353
* AMDGPU: Pattern match ffbh pattern to instruction.Matt Arsenault2016-01-111-20/+83
| | | | | | | | The hardware instruction's output on 0 is -1 rather than 32. Eliminate a test and select to -1. This removes an extra instruction from the compatability function with HSAIL's firstbit instruction. llvm-svn: 257352
* AMDGPU: Custom lower i64 ctlzMatt Arsenault2016-01-111-1/+58
| | | | llvm-svn: 257348
* LegalizeDAG: Expand ctlz with ctlz_zero_undef if legalMatt Arsenault2016-01-111-0/+3
| | | | llvm-svn: 257345
* AMDGPU: Use generic bitreverse intrinsicMatt Arsenault2015-12-141-4/+2
| | | | | | Also fix bug in vector legalization for bitreverse. llvm-svn: 255512
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