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* [AArch64][RegisterBankInfo] Bump the cost of vector loads.Quentin Colombet2016-10-131-0/+10
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284088
* [AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.Quentin Colombet2016-10-131-2/+11
| | | | | | | This does not change anything yet, because we do not offer any alternative mapping. llvm-svn: 284087
* [AArch64][RegisterBankInfo] Provide more realistic copy costs.Quentin Colombet2016-10-131-1/+10
| | | | llvm-svn: 284086
* GlobalISel: support G_TRUNC selection on AArch64.Tim Northover2016-10-121-0/+80
| | | | | | Ahmed's patch again. llvm-svn: 284075
* GlobalISel: support int <-> float conversions on AArch64.Tim Northover2016-10-121-1/+95
| | | | | | More of Ahmed's work. llvm-svn: 284074
* GlobalISel: select G_FCMP instructions on AArch64.Tim Northover2016-10-121-0/+116
| | | | | | Another of Ahmed's patches. llvm-svn: 284073
* GlobalISel: support selection of G_ICMP on AArch64.Tim Northover2016-10-121-0/+71
| | | | | | Patch from Ahmed Bougaca again. llvm-svn: 284072
* GlobalISel: select G_BRCOND instructions on AArch64.Tim Northover2016-10-121-0/+22
| | | | llvm-svn: 284071
* GlobalISel: mark G_BRCOND on s1 as legal.Tim Northover2016-10-121-3/+2
| | | | | | It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter. llvm-svn: 284070
* [AArch64][InstrustionSelector] Teach the selector about G_BITCAST.Quentin Colombet2016-10-121-59/+2
| | | | llvm-svn: 283973
* [AArch64][InstructionSelector] Refactor the handling of copies.Quentin Colombet2016-10-121-26/+83
| | | | | | | | | | | | | | Although Copies are not specific to preISel, we still have to assign them a proper register class. However, given they are not constrained to anything we do not have to handle the source register at the copy. It will be properly mapped when reaching the related definition. In the process, the handlong of G_ANYEXT is slightly modified as those end up being selected as copy. The difference is that when register size do not match on both sides, we need to insert SUBREG_TO_REG operation, otherwise the post RA copy expansion will not be happy! llvm-svn: 283972
* [AArch64][MachineLegalizer] Mark more bitcasts as legal.Quentin Colombet2016-10-121-0/+3
| | | | | | Those are copies, we do not have to do any legalization action for them. llvm-svn: 283970
* GlobalISel: support same-size casts on AArch64.Tim Northover2016-10-112-0/+75
| | | | | | | Mostly Ahmed's work again, I'm just sprucing things up slightly before committing. llvm-svn: 283952
* GlobalISel: support selection of extend operations.Tim Northover2016-10-111-0/+99
| | | | | | Patch mostly by Ahmed Bougaca. llvm-svn: 283937
* [AArch64] Allow label arithmetic with add/sub/cmpDiana Picus2016-10-113-26/+44
| | | | | | | | | | | | | Allow instructions such as 'cmp w0, #(end - start)' by folding the expression into a constant. For ELF, we fold only if the symbols are in the same section. For MachO, we fold if the expression contains only symbols that are not linker visible. Fixes https://llvm.org/bugs/show_bug.cgi?id=18920 Differential Revision: https://reviews.llvm.org/D23834 llvm-svn: 283862
* [AArch64][InstructionSelector] Teach how to select FP load/store.Quentin Colombet2016-10-111-0/+7
| | | | | | This patch allows to select 32 and 64-bit FP load and store. llvm-svn: 283832
* [AArch64][InstructionSelector] Teach the selector how to handle vector OR.Quentin Colombet2016-10-111-0/+2
| | | | | | | | | | This only adds the support for 64-bit vector OR. Adding more sizes is not difficult, but it requires a bigger refactoring because ORs work on any size, not necessarly the ones that match the width of the register width. Right now, this is not expressed in the legalization, so don't bother pushing the refactoring yet. llvm-svn: 283831
* [AArch64][MachineLegalizer] Mark v2s32 G_LOAD as legal.Quentin Colombet2016-10-111-1/+1
| | | | | | | Actually every 64-bit loads are legal, but right now the API does not offer a simple way to express that. llvm-svn: 283829
* Revert r283690, "MC: Remove unused entities."Peter Collingbourne2016-10-101-1/+1
| | | | llvm-svn: 283814
* GlobalISel: select G_GLOBAL_VALUE uses on AArch64.Tim Northover2016-10-103-4/+30
| | | | llvm-svn: 283809
* GlobalISel: allow G_GLOBAL_VALUEs in AArch64 legalization.Tim Northover2016-10-101-0/+1
| | | | llvm-svn: 283808
* GlobalISel: support selecting G_GEP instructions.Tim Northover2016-10-101-1/+3
| | | | | | They're basically just an alias for G_ADD on AArch64. llvm-svn: 283807
* GlobalISel: support selecting constants on AArch64.Tim Northover2016-10-101-0/+10
| | | | llvm-svn: 283806
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-097-31/+38
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* MC: Remove unused entities.Peter Collingbourne2016-10-091-1/+1
| | | | llvm-svn: 283691
* Target: Remove unused entities.Peter Collingbourne2016-10-093-13/+1
| | | | llvm-svn: 283690
* Turn cl::values() (for enum) from a vararg function to using C++ variadic ↵Mehdi Amini2016-10-081-2/+1
| | | | | | | | | | | | | | | template The core of the change is supposed to be NFC, however it also fixes what I believe was an undefined behavior when calling: va_start(ValueArgs, Desc); with Desc being a StringRef. Differential Revision: https://reviews.llvm.org/D25342 llvm-svn: 283671
* [AArch64] Avoid generating indexed vector instructions for ExynosSebastian Pop2016-10-084-0/+376
| | | | | | | | | | | | | | | | | | Avoid generating indexed vector instructions for Exynos. This is needed for fmla/fmls/fmul/fmulx. For example, the instruction fmla v0.4s, v1.4s, v2.s[1] is less efficient than the instructions dup v2.4s, v2.s[1] fmla v0.4s, v1.4s, v2.4s Patch written by Abderrazek Zaafrani. Differential Revision: https://reviews.llvm.org/D21571 llvm-svn: 283663
* Use StringReg in TargetParser APIs (NFC)Mehdi Amini2016-10-071-1/+1
| | | | llvm-svn: 283527
* Move AArch64BranchRelaxation to generic codeMatt Arsenault2016-10-064-421/+2
| | | | llvm-svn: 283459
* AArch64: Move remaining target specific BranchRelaxation bits to TIIMatt Arsenault2016-10-063-53/+37
| | | | llvm-svn: 283458
* AArch64: Macrofusion: Split features, add missing combinations.Matthias Braun2016-10-043-11/+59
| | | | | | | | | | | | | | | | AArch64InstrInfo::shouldScheduleAdjacent() determines whether two instruction can benefit from macroop fusion on apple CPUs. The list turned out to be incomplete: - the "rr" variants of the instructions were missing - even the "rs" variants can have shift value == 0 and behave like the "rr" variants This also splits the MacropFusion target feature into ArithmeticBccFusion and ArithmeticCbzFusion. Differential Revision: https://reviews.llvm.org/D25142 llvm-svn: 283243
* [AArch64][RegisterBankInfo] Add getSameKindofOperandsMapping.Quentin Colombet2016-10-032-26/+54
| | | | | | | | | | Refactor the code so that the same function can be used for all instructions with all the same operands for up to 3 operands. This is going to be useful for cast instructions. NFC. llvm-svn: 283144
* AArch64Subtarget: Remove unused CPUString fieldMatthias Braun2016-10-032-7/+6
| | | | llvm-svn: 283142
* Use StringRef in Datalayout API (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283013
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-0117-31/+17
| | | | llvm-svn: 283004
* Remove TargetTriple from AArch64MCInstLower as it's used in few placesEric Christopher2016-10-011-3/+4
| | | | | | and can be pulled from the TargetMachine. NFC. llvm-svn: 283000
* [AArch64][RegisterBankInfo] Use the helper functions for the checksQuentin Colombet2016-09-301-29/+26
| | | | | | | | This makes sure the helper functions work as expected. NFC. llvm-svn: 282961
* [AArch64][RegisterBankInfo] Rename getValueMappingIdx to getValueMappingQuentin Colombet2016-09-302-9/+11
| | | | | | | | We don't return index, we return the actual ValueMapping. NFC. llvm-svn: 282960
* [AArch64][RegisterBankInfo] Compress the ValueMapping table a bit.Quentin Colombet2016-09-302-46/+38
| | | | | | | | | | We don't need to have singleton ValueMapping on their own, we can just reuse one of the elements of the 3-ops mapping. This allows even more code sharing. NFC. llvm-svn: 282959
* [AArch64][RegisterBankInfo] Refactor the code to access AArch64::ValMappingQuentin Colombet2016-09-302-24/+23
| | | | | | | | | Use a helper function to access ValMapping. This should make the code easier to understand and maintain. NFC. llvm-svn: 282958
* [AArch64][RegisterBankInfo] Rename getRegBankIdx to getRegBankIdxOffsetQuentin Colombet2016-09-302-17/+22
| | | | | | | | | The function name did not make it clear that the returned value was an offset to apply to a register bank index. NFC. llvm-svn: 282957
* [AArch64][RegisterBankInfo] Use the static opds mapping for alt mappingsQuentin Colombet2016-09-301-14/+7
| | | | | | | | Avoid to rely on the dynamically allocated operands mapping for the alternative mapping. NFC. llvm-svn: 282956
* [AArch64][RegisterBankInfo] Use static mapping for 3-operands instrs.Quentin Colombet2016-09-301-0/+50
| | | | | | | | This uses a TableGen'ed like structure for all 3-operands instrs. The output of the RegBankSelect pass should be identical but the RegisterBankInfo will do less dynamic allocations. llvm-svn: 282817
* [AArch64][RegisterBankInfo] Add static value mapping for 3-op instrs.Quentin Colombet2016-09-302-12/+58
| | | | | | | This is the kind of input TableGen should generate at some point. NFC. llvm-svn: 282816
* [AArch64][RegisterBankInfo] Check the statically created ValueMapping.Quentin Colombet2016-09-301-0/+18
| | | | | | | | | Make sure that the ValueMappings contain the value we expect at the indices we expect. NFC. llvm-svn: 282815
* AArch64: Set shift bit of TLSLE HI12 add instructionLei Liu2016-09-291-0/+8
| | | | | | | | | | | | Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model. This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000. Reviewers: t.p.northover, peter.smith, rovka Subscribers: salim.nasser, aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D24702 llvm-svn: 282661
* [RegisterBankInfo] Uniquely generate OperandsMapping.Quentin Colombet2016-09-281-16/+27
| | | | | | | | | | | This is a step toward statically allocate InstructionMapping. Like the previous few commits, the goal is to move toward a TableGen'ed like structure with no dynamic allocation at all. This should already improve compile time by getting rid of a bunch of memmove of SmallVectors. llvm-svn: 282643
* [AArch64][RegisterBankInfo] Switch to statically allocated ValueMapping.Quentin Colombet2016-09-272-10/+24
| | | | | | | | Another step toward TableGen'ed like structure for the RegisterBankInfo of AArch64. By doing this, we also save a bit of compile time for the exact same output. llvm-svn: 282550
* [AArch64][RegisterBankInfo] Fix copy/paste in comments.Quentin Colombet2016-09-271-3/+3
| | | | | | NFC. llvm-svn: 282549
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