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* [FastISel][AArch64] Fold mul into the address computation of memory operations.Juergen Ributzka2014-09-171-0/+70
| | | | | | | | | Teach 'computeAddress' to also fold multiplies into the address computation (when possible). This fixes rdar://problem/18369443. llvm-svn: 217977
* [FastISel][AArch64] Fold compare with zero and branch into CBZ and CBNZ.Juergen Ributzka2014-09-171-0/+64
| | | | | | | | | This takes advanatage of the CBZ and CBNZ instruction to further optimize the common null check pattern into a single instruction. This is related to rdar://problem/18358882. llvm-svn: 217972
* [FastISel][AArch64] Improve branch selection to support all FP conditions.Juergen Ributzka2014-09-171-10/+48
| | | | | | | | | | | | This adds the last two missing floating-point condition codes (FCMP_UEQ and FCMP_ONE) also to the branch selection. In these two cases an additonal branch instruction is required. This also adds unit tests to checks all the different condition codes. This is related o rdar://problem/18358882. llvm-svn: 217966
* [X86] Use the generic AtomicExpandPass instead of X86AtomicExpandPassRobin Morisset2014-09-172-0/+5
| | | | | | | | | | | | This required a new hook called hasLoadLinkedStoreConditional to know whether to expand atomics to LL/SC (ARM, AArch64, in a future patch Power) or to CmpXchg (X86). Apart from that, the new code in AtomicExpandPass is mostly moved from X86AtomicExpandPass. The main result of this patch is to get rid of that pass, which had lots of code duplicated with AtomicExpandPass. llvm-svn: 217928
* [FastISel][AArch64] Add vector support to argument lowering.Juergen Ributzka2014-09-161-42/+44
| | | | | | Lower the first 8 vector arguments too. llvm-svn: 217850
* [FastISel][AArch64] Allow handling of vectors during return lowering for ↵Juergen Ributzka2014-09-151-2/+7
| | | | | | | | | | little endian machines. Allow handling of vectors during return lowering at least for little endian machines. This was restricted in r208200 to fix it for big endian machines (according to the comment), but it also disabled it for little endian too. llvm-svn: 217846
* [FastISel][AArch64] Update function and variable names to follow the coding ↵Juergen Ributzka2014-09-151-164/+162
| | | | | | standard. NFC. llvm-svn: 217845
* [FastISel][AArch64] Make AArch64FastISel class final. NFC.Juergen Ributzka2014-09-151-1/+1
| | | | llvm-svn: 217840
* [FastISel][AArch64] Lower sin/cos/pow to runtime lib calls.Juergen Ributzka2014-09-151-0/+50
| | | | | | | | Also lower sin/cos/pow to runtime lib calls. This fixes rdar://problem/18343468. llvm-svn: 217839
* [FastISel][AArch64] Add lowering support for frem.Juergen Ributzka2014-09-151-1/+44
| | | | | | | | | | | This lowers frem to a runtime libcall inside fast-isel. The test case also checks the CallLoweringInfo bug that was exposed by this change. This fixes rdar://problem/18342783. llvm-svn: 217833
* [FastISel][AArch64] Refactor selectAddSub, selectLogicalOp, and SelectShift. ↵Juergen Ributzka2014-09-151-27/+41
| | | | | | | | NFC. Small refactor to tidy up the code a little. llvm-svn: 217827
* [FastISel][AArch64] Refactor code to use isTypeSupported. NFC.Juergen Ributzka2014-09-151-19/+6
| | | | | | Gets rid of isLoadStoreTypeLegal and replace it with isTypeSupported. llvm-svn: 217826
* [FastISel][AArch64] Improve floating-point compare support.Juergen Ributzka2014-09-151-7/+62
| | | | | | | | Add support for the last two missing fcmp condition codes: UEQ and ONE. This fixes rdar://problem/18341575. llvm-svn: 217823
* [A57FPLoadBalancing] Modify r217689 - actually we do need to check defsJames Molloy2014-09-141-6/+6
| | | | | | | | ... Just make sure we check uses first so we see the kill first. It turns out ignoring defs gives some pretty nasty runtime failures. I'm certain this is the fix but I'm still reducing a testcase. llvm-svn: 217735
* [FastISel][AArch64] Add support for non-native types for logical ops.Juergen Ributzka2014-09-131-36/+48
| | | | | | | | | Extend the logical ops selection to also support non-native types such as i1, i8, and i16. Fixes rdar://problem/18330589. llvm-svn: 217732
* [AArch64] Don't enable the post-RA MI scheduler at OptNone.Chad Rosier2014-09-121-1/+2
| | | | | | Hopefully, this will appease the bots. llvm-svn: 217712
* [AArch64] Enable post-RA MI scheduler.Chad Rosier2014-09-122-1/+6
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5278 Patch by Sanjin Sijaric! llvm-svn: 217693
* [A57FPLoadBalancing] Remove support for vector typesJames Molloy2014-09-121-5/+0
| | | | | | | | Vector MUL/MLAs have tied operands, which gives us extra constraints that we currently can't handle. Instead of silently doing the wrong thing, remove support to be readded later properly. llvm-svn: 217690
* [A57FPLoadBalancing] Ignore <def>s when checking if a chain may be killed.James Molloy2014-09-121-0/+4
| | | | | | | | Defs are seen before uses, so a def without the kill flag doesn't necessarily mean that the register is not killed on that instruction. It may be killed in a later use operand. llvm-svn: 217689
* [A57LoadBalancing] unique_ptr-ify.James Molloy2014-09-121-25/+20
| | | | | | Thanks to David Blakie for the in-depth review! llvm-svn: 217682
* Fix gcc -Wpedantic.Patrik Hagglund2014-09-121-1/+1
| | | | llvm-svn: 217669
* [AArch64] Revert r216141 for cycloneGerolf Hoflehner2014-09-101-1/+1
| | | | | | | | | | The increase of the interleave factor to 4 has side-effects like performance losses eg. due to reminder loops being executed more frequently and may increase code size. It requires more analysis and careful heuristic tuning. Expect double digit gains in small benchmarks like lowercase.c and losses in puzzle.c. llvm-svn: 217540
* Rename getMaximumUnrollFactor -> getMaxInterleaveFactor; also rename option ↵Sanjay Patel2014-09-101-2/+2
| | | | | | | | | | | names controlling this variable. "Unroll" is not the appropriate name for this variable. Clang already uses the term "interleave" in pragmas and metadata for this. Differential Revision: http://reviews.llvm.org/D5066 llvm-svn: 217528
* [AArch64] Address Chad's post commit review comments for r217504 (PBQP ↵Arnaud A. de Grandmaison2014-09-101-11/+10
| | | | | | experimental support) llvm-svn: 217518
* [AArch64] Pacify lld buildbot complaining about an unused static function in ↵Arnaud A. de Grandmaison2014-09-101-0/+2
| | | | | | release build. llvm-svn: 217505
* [AArch64] Add experimental PBQP supportArnaud A. de Grandmaison2014-09-105-2/+435
| | | | | | | | | | This adds target specific support for using the PBQP register allocator on the AArch64, for the A57 cpu. By default, the PBQP allocator is not used, unless explicitely required on the command line with "-aarch64-pbqp". llvm-svn: 217504
* [AArch 64] Use a constant pool load for weak symbol references whenAsiri Rathnayake2014-09-104-6/+39
| | | | | | | | | | | | | | using static relocation model and small code model. Summary: currently we generate GOT based relocations for weak symbol references regardless of the underlying relocation model. This should be change so that in static relocation model we use a constant pool load instead. Patch from: Keith Walker Reviewers: Renato Golin, Tim Northover llvm-svn: 217503
* [AArch64] Enabled AA support for Cortex-A57.Chad Rosier2014-09-081-1/+1
| | | | llvm-svn: 217381
* [AArch64] Improve AA to remove unneeded edges in the AA MI scheduling graph.Chad Rosier2014-09-082-0/+140
| | | | | | | Patch by Sanjin Sijaric <ssijaric@codeaurora.org>! Phabricator Review: http://reviews.llvm.org/D5103 llvm-svn: 217371
* [AArch64] Enabled AA support for Cortex-A53.Chad Rosier2014-09-081-0/+2
| | | | | | | Patch by Sanjin Sijaric <ssijaric@codeaurora.org>! Phabricator Review: http://reviews.llvm.org/D5103 llvm-svn: 217370
* [AArch64] Add pass to enable additional comparison optimizations by CSE.Jiangning Liu2014-09-054-0/+414
| | | | | | | | | | | | | | | | | | Patched by Sergey Dmitrouk. This pass tries to make consecutive compares of values use same operands to allow CSE pass to remove duplicated instructions. For this it analyzes branches and adjusts comparisons with immediate values by converting: GE -> GT GT -> GE LT -> LE LE -> LT and adjusting immediate values appropriately. It basically corrects two immediate values towards each other to make them equal. llvm-svn: 217220
* AArch64: fix vector-immediate BIC/ORR on big-endian devices.Tim Northover2014-09-042-12/+24
| | | | | | | | | | Follow up to r217138, extending the logic to other NEON-immediate instructions. As before, the instruction already performs the correct operation and we're just using a different type for convenience, so we want a true nop-cast. Patch by Asiri Rathnayake. llvm-svn: 217159
* AArch64: fix big-endian immediate materialisationTim Northover2014-09-043-21/+82
| | | | | | | | | | | | We were materialising big-endian constants using DAG nodes with types different from what was requested, followed by a bitcast. This is fine on little-endian machines where bitcasting is a nop, but we need a slightly different representation for big-endian. This adds a new set of NVCAST (natural-vector cast) operations which are always nops. Patch by Asiri Rathnayake. llvm-svn: 217138
* [FastISel][AArch64] Cleanup and simplify 'fastSelectInstruction'. NFC.Juergen Ributzka2014-09-041-75/+12
| | | | llvm-svn: 217119
* [FastISel][AArch64] Add target-specific lowering for logical operations.Juergen Ributzka2014-09-041-26/+163
| | | | | | | | | This change adds support for immediate and shift-left folding into logical operations. This fixes rdar://problem/18223183. llvm-svn: 217118
* Refactor AtomicExpandPass and add a generic isAtomic() method to InstructionRobin Morisset2014-09-032-14/+25
| | | | | | | | | | | | | | | | | | | | | Summary: Split shouldExpandAtomicInIR() into different versions for Stores/Loads/RMWs/CmpXchgs. Makes runOnFunction cleaner (no more redundant checking/casting), and will help moving the X86 backend to this pass. This requires a way of easily detecting which instructions are atomic. I followed the pattern of mayReadFromMemory, mayWriteOrReadMemory, etc.. in making isAtomic() a method of Instruction implemented by a switch on the opcodes. Test Plan: make check Reviewers: jfb Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5035 llvm-svn: 217080
* [FastISel][tblgen] Rename tblgen generated FastISel functions. NFC.Juergen Ributzka2014-09-031-33/+33
| | | | | | | | | | This is the final round of renaming. This changes tblgen to emit lower-case function names for FastEmitInst_* and FastEmit_*, and updates all its uses in the source code. Reviewed by Eric llvm-svn: 217075
* [FastISel] Rename public visible FastISel functions. NFC.Juergen Ributzka2014-09-031-43/+43
| | | | | | | | | | | | | | | | | | | | | This commit renames the following public FastISel functions: LowerArguments -> lowerArguments SelectInstruction -> selectInstruction TargetSelectInstruction -> fastSelectInstruction FastLowerArguments -> fastLowerArguments FastLowerCall -> fastLowerCall FastLowerIntrinsicCall -> fastLowerIntrinsicCall FastEmitZExtFromI1 -> fastEmitZExtFromI1 FastEmitBranch -> fastEmitBranch UpdateValueMap -> updateValueMap TargetMaterializeConstant -> fastMaterializeConstant TargetMaterializeAlloca -> fastMaterializeAlloca TargetMaterializeFloatZero -> fastMaterializeFloatZero LowerCallTo -> lowerCallTo Reviewed by Eric llvm-svn: 217074
* Remove unnecessary getTarget call now that the subtarget is cachedEric Christopher2014-09-031-1/+1
| | | | | | on the machine function. llvm-svn: 217070
* [FastISel] Some long overdue spring cleaning of FastISel.Juergen Ributzka2014-09-031-30/+30
| | | | | | | | | | | | | Things got a little bit messy over the years and it is time for a little bit spring cleaning. This first commit is focused on the FastISel base class itself. It doxyfies all comments, C++11fies the code where it makes sense, renames internal methods to adhere to the coding standard, and clang-formats the files. Reviewed by Eric llvm-svn: 217060
* [FastISel][AArch64] Move unconditional branch handling into 'SelectBranch'. NFC.Juergen Ributzka2014-09-031-9/+7
| | | | llvm-svn: 217054
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-034-10/+11
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-09-031-79/+128
| | | | | | | | | | | | | | | | for MADD, SUB, and OR."" This reapplies r216805 with a fix to a copy-past error, which resulted in an incorrect register class. Original commit message: Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 217019
* [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub.Juergen Ributzka2014-09-031-187/+164
| | | | | | | | | | | There is already target-dependent instruction selection support for Adds/Subs to support compares and the intrinsics with overflow check. This takes advantage of the existing infrastructure to also support Add/Sub, which allows the folding of immediates, sign-/zero-extends, and shifts. This fixes rdar://problem/18207316. llvm-svn: 217007
* [FastISel][AArch64] Use the target-dependent selection code for shifts first.Juergen Ributzka2014-09-021-6/+6
| | | | | | | | | | | | This uses the target-dependent selection code for shifts first, which allows us to create better code for shifts with immediates and sign-/zero-extend folding. Vector type are not handled yet and the code falls back to target-independent instruction selection for these cases. This fixes rdar://problem/17907920. llvm-svn: 216985
* [FastISel][AArch64] Use a new helper function to determine if a value type ↵Juergen Ributzka2014-09-021-6/+25
| | | | | | | | | | | | is supported. NFCI. FastISel for AArch64 supports more value types than are actually legal. Use a dedicated helper function to reflect this. It is very similar to the isLoadStoreTypeLegal function, with the exception that vector types are not supported yet. llvm-svn: 216984
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-1/+1
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* [FastISel][AArch64] Move over to target-dependent instruction selection only.Juergen Ributzka2014-09-021-41/+133
| | | | | | | | | | | This change moves FastISel for AArch64 to target-dependent instruction selection only. This change replicates the existing target-independent behavior, therefore there are no changes to the unit tests or new tests. Future changes will take advantage of this change and update functionality and unit tests. llvm-svn: 216955
* Change MCSchedModel to be a struct of statically initialized data.Pete Cooper2014-09-022-3/+3
| | | | | | | | This removes static initializers from the backends which generate this data, and also makes this struct match the other Tablegen generated structs in behaviour Reviewed by Andy Trick and Chandler C llvm-svn: 216919
* Fix left shifts of negative integers in AArch64 InstPrinter/DisassemblerAlexey Samsonov2014-09-022-5/+5
| | | | | | | | | | | | | | | | | | | Summary: Left shift of negative integer is an undefined behavior, and is reported by UBSan. It's ok for imm values to be negative, so we can just replace left shifts with multiplications. Test Plan: check-llvm test suite Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5132 llvm-svn: 216910
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