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* AArch64: Canonicalize access to function attributes, NFCDuncan P. N. Exon Smith2015-02-145-19/+10
| | | | | | | | | | | | Canonicalize access to function attributes to use the simpler API. getAttributes().getAttribute(AttributeSet::FunctionIndex, Kind) => getFnAttribute(Kind) getAttributes().hasAttribute(AttributeSet::FunctionIndex, Kind) => hasFnAttribute(Kind) llvm-svn: 229218
* [PM] Remove the old 'PassManager.h' header file at the top level ofChandler Carruth2015-02-131-1/+1
| | | | | | | | | | | | | | | | | | | | LLVM's include tree and the use of using declarations to hide the 'legacy' namespace for the old pass manager. This undoes the primary modules-hostile change I made to keep out-of-tree targets building. I sent an email inquiring about whether this would be reasonable to do at this phase and people seemed fine with it, so making it a reality. This should allow us to start bootstrapping with modules to a certain extent along with making it easier to mix and match headers in general. The updates to any code for users of LLVM are very mechanical. Switch from including "llvm/PassManager.h" to "llvm/IR/LegacyPassManager.h". Qualify the types which now produce compile errors with "legacy::". The most common ones are "PassManager", "PassManagerBase", and "FunctionPassManager". llvm-svn: 229094
* Learn that __DATA,__objc_classrefs is not atomized via symbols.Rafael Espindola2015-02-121-0/+4
| | | | | | This should hopefully fix objc on AArch64. llvm-svn: 228976
* MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line ↵Benjamin Kramer2015-02-123-9/+9
| | | | | | | | with countTrailingZeros Update all callers. llvm-svn: 228930
* [PBQP] Cautiously update edge costs in the solverArnaud A. de Grandmaison2015-02-111-2/+2
| | | | | | | | | | | | | | | | | | The NodeMetadata are maintained in an incremental way. When an edge between 2 nodes has its cost updated, in the course of graph reduction for example, the NodeMetadata need first to have the old edge cost removed, then the new edge cost added. Only once the NodeMetadata have been fully updated, it becomes safe to consider promoting the nodes to the ConservativelyAllocatable or OptimallyReducible sets. Previously, this promotion was occuring right after the removing the old cost, and this was breaking the assumption that a ConservativelyAllocatable should not be spilled. This patch also adds asserts to: - enforces the invariant that a node's reduction can not be downgraded, - only not provably allocatable or optimally reducible nodes can be spilled. llvm-svn: 228816
* ARM & AArch64: teach LowerVSETCC that output type size may differ from input.Tim Northover2015-02-081-5/+11
| | | | | | | | | | | | | | | | | | While various DAG combines try to guarantee that a vector SETCC operation will have the same output size as input, there's nothing intrinsic to either creation or LegalizeTypes that actually guarantees it, so the function needs to be ready to handle a mismatch. Fortunately this is easy enough, just extend or truncate the naturally compared result. I couldn't reproduce the failure in other backends that I know have SIMD, so it's probably only an issue for these two due to shared heritage. Should fix PR21645. llvm-svn: 228518
* [AArch64] Use the source location of the IR branch when creating BccAhmed Bougacha2015-02-061-2/+2
| | | | | | | | | | | | | | | | | | from a conditional branch fed by an add/sub/mul-with-overflow node. We previously used the SDLoc of the overflow node, for no good reason. In some cases, this led to the Bcc and B terminators having different source orders, and DBG_VALUEs being inserted between them. The real issue is with the code that can't handle DBG_VALUEs between terminators: the few places affected by this will be fixed soon. In the meantime, fixing the SDLoc is a positive change no matter what. No tests, as I have no idea how to get .loc emitted for branches? rdar://19347133 llvm-svn: 228463
* AArch64PromoteConstant: Modernize and resolve some Use<->User confusion.Benjamin Kramer2015-02-061-87/+63
| | | | | | NFC. llvm-svn: 228399
* Adding support to LLVM for targeting Cortex-A72Renato Golin2015-02-041-0/+2
| | | | | | | | | | Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. llvm-svn: 228140
* Fix some unnoticed/unwanted behavior change from r222319.Frederic Riss2015-02-041-1/+1
| | | | | | | | | The ARM assembler allows register alias redefinitions as long as it targets the same register. r222319 broke that. In the AArch64 case it would just produce a new warning, but in the ARM case it would error out on previously accepted assembler. llvm-svn: 228109
* Migrate away from using a Subtarget except for the one place we wantEric Christopher2015-02-031-12/+7
| | | | | | | to use it. Use the triple to determine OS format bits at the module level. llvm-svn: 227947
* [AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.Ahmed Bougacha2015-02-021-14/+6
| | | | | | | | | This avoids a partial false dependency on the previous content of the upper lanes of the destination vector register. Differential Revision: http://reviews.llvm.org/D7307 llvm-svn: 227820
* [multiversion] Remove the function parameter from the unrollingChandler Carruth2015-02-012-3/+2
| | | | | | preferences interface on TTI now that all of TTI is per-function. llvm-svn: 227741
* [multiversion] Switch the TTI queries from TargetMachine to SubtargetChandler Carruth2015-02-011-1/+1
| | | | | | | | | | | | | | | | | | | now that we have a correct and cached subtarget specific to the function. Also, finish providing a cached per-function subtarget in the core LLVMTargetMachine -- that layer hadn't switched over yet. The only use of the TargetMachine was to re-lookup a subtarget for a particular function to work around the fact that TTI was immutable. Now that it is per-function and we haved a cached subtarget, use it. This still leaves a few interfaces with real warts on them where we were passing Function objects through the TTI interface. I'll remove these and clean their usage up in subsequent commits now that this isn't necessary. llvm-svn: 227738
* [multiversion] Remove the cached TargetMachine pointer from theChandler Carruth2015-02-011-4/+13
| | | | | | | | | | | | | | | | intermediate TTI implementation template and instead query up to the derived class for both the TargetMachine and the TargetLowering. Most of the derived types had a TLI cached already and there is no need to store a less precisely typed target machine pointer. This will in turn make it much cleaner to look up the TLI via a per-function subtarget instead of the generic subtarget, and it will pave the way toward pulling the subtarget used for unroll preferences into the same form once we are *always* using the function to look up the correct subtarget. llvm-svn: 227737
* [multiversion] Switch all of the targets over to use theChandler Carruth2015-02-013-6/+8
| | | | | | | | | | | | | | | | TargetIRAnalysis access path directly rather than implementing getTTI. This even removes getTTI from the interface. It's more efficient for each target to just register a precise callback that creates their specific TTI. As part of this, all of the targets which are building their subtargets individually per-function now build their TTI instance with the function and thus look up the correct subtarget and cache it. NVPTX, R600, and XCore currently don't leverage this functionality, but its trivial for them to add it now. llvm-svn: 227735
* [multiversion] Remove a false freedom to leave the TargetMachine pointerChandler Carruth2015-02-011-3/+2
| | | | | | | | | | | | | | | | | null. For some reason some of the original TTI code supported a null target machine. This seems to have been legacy, and I made matters worse when refactoring this code by spreading that pattern further through the various targets. The TargetMachine can't actually be null, and it doesn't make sense to support that use case. I've now consistently removed it and removed all of the code trying to cope with that situation. This is probably good, as several targets *didn't* cope with it being null despite the null default argument in their constructors. =] llvm-svn: 227734
* [PM] Remove a bunch of stale TTI creation method declarations. I nukedChandler Carruth2015-02-011-3/+0
| | | | | | | their definitions, but forgot to clean up all the declarations which are in different files. llvm-svn: 227698
* [PM] Switch the TargetMachine interface from accepting a pass managerChandler Carruth2015-01-314-131/+146
| | | | | | | | | | | | | | | | | | | | | | | base which it adds a single analysis pass to, to instead return the type erased TargetTransformInfo object constructed for that TargetMachine. This removes all of the pass variants for TTI. There is now a single TTI *pass* in the Analysis layer. All of the Analysis <-> Target communication is through the TTI's type erased interface itself. While the diff is large here, it is nothing more that code motion to make types available in a header file for use in a different source file within each target. I've tried to keep all the doxygen comments and file boilerplate in line with this move, but let me know if I missed anything. With this in place, the next step to making TTI work with the new pass manager is to introduce a really simple new-style analysis that produces a TTI object via a callback into this routine on the target machine. Once we have that, we'll have the building blocks necessary to accept a function argument as well. llvm-svn: 227685
* [PM] Change the core design of the TTI analysis to use a polymorphicChandler Carruth2015-01-312-121/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type erased interface and a single analysis pass rather than an extremely complex analysis group. The end result is that the TTI analysis can contain a type erased implementation that supports the polymorphic TTI interface. We can build one from a target-specific implementation or from a dummy one in the IR. I've also factored all of the code into "mix-in"-able base classes, including CRTP base classes to facilitate calling back up to the most specialized form when delegating horizontally across the surface. These aren't as clean as I would like and I'm planning to work on cleaning some of this up, but I wanted to start by putting into the right form. There are a number of reasons for this change, and this particular design. The first and foremost reason is that an analysis group is complete overkill, and the chaining delegation strategy was so opaque, confusing, and high overhead that TTI was suffering greatly for it. Several of the TTI functions had failed to be implemented in all places because of the chaining-based delegation making there be no checking of this. A few other functions were implemented with incorrect delegation. The message to me was very clear working on this -- the delegation and analysis group structure was too confusing to be useful here. The other reason of course is that this is *much* more natural fit for the new pass manager. This will lay the ground work for a type-erased per-function info object that can look up the correct subtarget and even cache it. Yet another benefit is that this will significantly simplify the interaction of the pass managers and the TargetMachine. See the future work below. The downside of this change is that it is very, very verbose. I'm going to work to improve that, but it is somewhat an implementation necessity in C++ to do type erasure. =/ I discussed this design really extensively with Eric and Hal prior to going down this path, and afterward showed them the result. No one was really thrilled with it, but there doesn't seem to be a substantially better alternative. Using a base class and virtual method dispatch would make the code much shorter, but as discussed in the update to the programmer's manual and elsewhere, a polymorphic interface feels like the more principled approach even if this is perhaps the least compelling example of it. ;] Ultimately, there is still a lot more to be done here, but this was the huge chunk that I couldn't really split things out of because this was the interface change to TTI. I've tried to minimize all the other parts of this. The follow up work should include at least: 1) Improving the TargetMachine interface by having it directly return a TTI object. Because we have a non-pass object with value semantics and an internal type erasure mechanism, we can narrow the interface of the TargetMachine to *just* do what we need: build and return a TTI object that we can then insert into the pass pipeline. 2) Make the TTI object be fully specialized for a particular function. This will include splitting off a minimal form of it which is sufficient for the inliner and the old pass manager. 3) Add a new pass manager analysis which produces TTI objects from the target machine for each function. This may actually be done as part of #2 in order to use the new analysis to implement #2. 4) Work on narrowing the API between TTI and the targets so that it is easier to understand and less verbose to type erase. 5) Work on narrowing the API between TTI and its clients so that it is easier to understand and less verbose to forward. 6) Try to improve the CRTP-based delegation. I feel like this code is just a bit messy and exacerbating the complexity of implementing the TTI in each target. Many thanks to Eric and Hal for their help here. I ended up blocked on this somewhat more abruptly than I expected, and so I appreciate getting it sorted out very quickly. Differential Revision: http://reviews.llvm.org/D7293 llvm-svn: 227669
* Avoid using the cast and use the templated accessor function.Eric Christopher2015-01-301-1/+1
| | | | llvm-svn: 227643
* [AArch64] Make AArch64A57FPLoadBalancing output stable.Chad Rosier2015-01-301-2/+9
| | | | | | | | | | | | | Add tie breaker to colorChainSet() sort so that processing order doesn't depend on std::set order, which depends on pointer order, which is unstable from run to run. No test case as this is nearly impossible to reproduce. Phabricator Review: http://reviews.llvm.org/D7265 Patch by Geoff Berry <gberry@codeaurora.org>! llvm-svn: 227606
* [AArch64]Fix PR21675, a bug about lowering llvm.ctpop.i32. We should noot ↵Hao Liu2015-01-301-10/+4
| | | | | | | | use "DAG.getUNDEF(MVT::v8i8)" to get all zero vector. Patch by Wei-cheng Wang. llvm-svn: 227550
* Remove a few getSubtarget calls in AArch64 pass manager initialization.Eric Christopher2015-01-301-2/+2
| | | | llvm-svn: 227531
* Clean up some uses of getSubtarget in AArch64.Eric Christopher2015-01-306-23/+12
| | | | llvm-svn: 227530
* This only needs TargetInstrInfo, not the specialized one.Eric Christopher2015-01-301-3/+3
| | | | llvm-svn: 227529
* [AArch64] Add INITIALIZE_PASS macros to AArch64A57FPLoadBalancing.Chad Rosier2015-01-291-1/+15
| | | | | | | | | | These are needed so this pass will produce output when e.g. -print-after-all is used. Phabricator Review: http://reviews.llvm.org/D7264 Patch by Geoff Berry <gberry@codeaurora.org>! llvm-svn: 227506
* Remove getSubtargetImpl from AArch64ISelLowering and cache theEric Christopher2015-01-293-13/+10
| | | | | | | correct subtarget by passing it in during the constructor as TargetLowering is Subtarget specific. llvm-svn: 227402
* fix typos; NFCSanjay Patel2015-01-282-2/+2
| | | | llvm-svn: 227386
* Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.Eric Christopher2015-01-2810-48/+29
| | | | llvm-svn: 227293
* Clean up the AArch64 store pair suppression pass initializationEric Christopher2015-01-271-11/+7
| | | | | | and remove and unnecessary class variable. llvm-svn: 227175
* The subtarget is cached on the MachineFunction. Access it directly.Eric Christopher2015-01-272-4/+2
| | | | llvm-svn: 227173
* Commoning of target specific load/store intrinsics in Early CSE.Chad Rosier2015-01-261-0/+91
| | | | | | | Phabricator revision: http://reviews.llvm.org/D7121 Patch by Sanjin Sijaric <ssijaric@codeaurora.org>! llvm-svn: 227149
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-268-19/+21
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* Fix a problem where the AArch64 ELF assembler was failing withEric Christopher2015-01-261-1/+2
| | | | | | | | | -no-exec-stack. This was due to it not deriving from the correct asm info base class and missing the override for the exec stack section query. Added another line to the noexec test line to make sure this doesn't regress. llvm-svn: 227074
* [AArch64][LoadStoreOptimizer] Form LDPSW when possible.Quentin Colombet2015-01-241-1/+15
| | | | | | | | | This patch adds the missing LD[U]RSW variants to the load store optimizer, so that we generate LDPSW when possible. <rdar://problem/19583480> llvm-svn: 226978
* AArch64: decode all MRS/MSR forms early to avoid saving FeatureBits.Tim Northover2015-01-221-42/+35
| | | | | | | | | | | | Currently, we're adding a uint64_t describing the current subtarget so that matching can check whether the specified register is valid. However, we want to move to a bitset for those bits (x86 has more than 64 of them). This can't live in a union so it's probably better to do the checks early (especially as there are only 3 of them). llvm-svn: 226841
* AArch64: add backend option to reserve x18 (platform register)Tim Northover2015-01-211-3/+7
| | | | | | | | | AAPCS64 says that it's up to the platform to specify whether x18 is reserved, and a first step on that way is to add a flag controlling it. From: Andrew Turner <andrew@fubar.geek.nz> llvm-svn: 226664
* Add r224985 back with fixes.Rafael Espindola2015-01-192-68/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fixes are to note that AArch64 has additional restrictions on when local relocations can be used. In particular, ld64 requires that relocations to cstring/cfstrings use linker visible symbols. Original message: In an assembly expression like bar: .long L0 + 1 the intended semantics is that bar will contain a pointer one byte past L0. In sections that are merged by content (strings, 4 byte constants, etc), a single position in the section doesn't give the linker enough information. For example, it would not be able to tell a relocation must point to the end of a string, since that would look just like the start of the next. The solution used in ELF to use relocation with symbols if there is a non-zero addend. In MachO before this patch we would just keep all symbols in some sections. This would miss some cases (only cstrings on x86_64 were implemented) and was inefficient since most relocations have an addend of 0 and can be represented without the symbol. This patch implements the non-zero addend logic for MachO too. llvm-svn: 226503
* [AArch64] Implement GHC calling conventionGreg Fitzgerald2015-01-195-1/+62
| | | | | | | | | | Original patch by Luke Iannini. Minor improvements and test added by Erik de Castro Lopo. Differential Revision: http://reviews.llvm.org/D6877 From: Erik de Castro Lopo <erikd@mega-nerd.com> llvm-svn: 226473
* unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizerDavid Blaikie2015-01-181-7/+5
| | | | llvm-svn: 226416
* std::unique_ptrify the MCStreamer argument to createAsmPrinterDavid Blaikie2015-01-181-2/+2
| | | | llvm-svn: 226414
* Revert "Add r224985 back with two fixes."Rafael Espindola2015-01-142-46/+68
| | | | | | This reverts commit r225644 while I debug a regression. llvm-svn: 226022
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-144-4/+4
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* Add r224985 back with two fixes.Rafael Espindola2015-01-122-68/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One is that AArch64 has additional restrictions on when local relocations can be used. We have to take those into consideration when deciding to put a L symbol in the symbol table or not. The other is that ld64 requires the relocations to cstring to use linker visible symbols on AArch64. Thanks to Michael Zolotukhin for testing this! Remove doesSectionRequireSymbols. In an assembly expression like bar: .long L0 + 1 the intended semantics is that bar will contain a pointer one byte past L0. In sections that are merged by content (strings, 4 byte constants, etc), a single position in the section doesn't give the linker enough information. For example, it would not be able to tell a relocation must point to the end of a string, since that would look just like the start of the next. The solution used in ELF to use relocation with symbols if there is a non-zero addend. In MachO before this patch we would just keep all symbols in some sections. This would miss some cases (only cstrings on x86_64 were implemented) and was inefficient since most relocations have an addend of 0 and can be represented without the symbol. This patch implements the non-zero addend logic for MachO too. llvm-svn: 225644
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 llvm-svn: 225421
* [CodeGen] Use MVT iterator_ranges in legality loops. NFC intended.Ahmed Bougacha2015-01-071-20/+15
| | | | | | | | A few loops do trickier things than just iterating on an MVT subset, so I'll leave them be for now. Follow-up of r225387. llvm-svn: 225392
* Revert r225165 and r225169Karthik Bhat2015-01-071-39/+0
| | | | | | | | Even thouh gcc produces simialr instructions as Owen pointed out the two patterns aren’t equivalent in the case where the original subtraction could have caused an overflow. Reverting the same. llvm-svn: 225341
* Revert r225048: It broke ObjC on AArch64.Lang Hames2015-01-062-32/+68
| | | | | | I've filed http://llvm.org/PR22100 to track this issue. llvm-svn: 225228
* [AArch64] Improve codegen of store lane instructions by avoiding GPR usage.Ahmed Bougacha2015-01-051-2/+2
| | | | | | | | | | | | | | | | | | | | We used to generate code similar to: umov.b w8, v0[2] strb w8, [x0, x1] because the STR*ro* patterns were preferred to ST1*. Instead, we can avoid going through GPRs, and generate: add x8, x0, x1 st1.b { v0 }[2], [x8] This patch increases the ST1* AddedComplexity to achieve that. rdar://16372710 Differential Revision: http://reviews.llvm.org/D6202 llvm-svn: 225183
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