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* [AArch64][v8.1a] The "pan" sysreg isn't MSR-specific. NFCI.Ahmed Bougacha2015-08-041-3/+0
| | | | | | | It's already in SysRegMappings, no need to also have it in MSRMappings: the latter is only used if we didn't find a match in the former. llvm-svn: 243933
* ARM]: Add support for MMFR4_EL1 in assemblerJaved Absar2015-06-081-0/+1
| | | | | | | This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler. This register provides information about the implemented memory model and memory management support. llvm-svn: 239302
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-707/+708
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-708/+707
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-707/+708
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* [AArch64] LORID_EL1 register must be treated as read-onlyVladimir Sukharev2015-04-201-3/+5
| | | | | | | | | | | | Patch by: John Brawn Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9105 llvm-svn: 235314
* [AArch64] Add v8.1a "Virtualization Host Extensions"Vladimir Sukharev2015-04-161-1/+30
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8500 Patch by: Tom Coxon llvm-svn: 235107
* [AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev2015-04-161-0/+7
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8499 Patch by: Tom Coxon llvm-svn: 235105
* [AArch64] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-161-2/+11
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8498 llvm-svn: 235104
* [AArch64] Handle Cyclone-specific register in common wayVladimir Sukharev2015-04-161-24/+3
| | | | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8584 Patch by: Tom Coxon llvm-svn: 235102
* [AArch64] Follow-up to: Refactor AArch64NamedImmMapper to become dependent ↵Vladimir Sukharev2015-04-161-665/+665
| | | | | | | | | | on subtarget features Fixed compilation with clang on some buildbots with "-Werror -Wmissing-field-initializers" Related to: http://reviews.llvm.org/rL235089 llvm-svn: 235099
* [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget ↵Vladimir Sukharev2015-04-161-8/+10
| | | | | | | | | | | | | | | | | | | | | | features. In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available. This patch introduces refactoring, that will then allow to easily introduce: - v8.1-specific "pan" PState for PStateMapper (PAN extension) - v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions) Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8496 Patch by Tom Coxon llvm-svn: 235089
* [AArch64] Don't store available subtarget features in ↵Vladimir Sukharev2015-03-271-6/+5
| | | | | | | | | | | | | | AArch64SysReg::SysRegMapper Subtarget features must not be a part of the target machine. So, they are now not being stored in SysRegMapper, but provided each time fromString()/toString() are called Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8655 llvm-svn: 233386
* [AArch64] Rename Pairs to Mappings in AArch64NamedImmMapperVladimir Sukharev2015-03-261-48/+48
| | | | | | | | | | | | Third element is to be added soon to "struct AArch64NamedImmMapper::Mapping". So its instances are renamed from ...Pairs to ...Mappings Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8582 llvm-svn: 233300
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-5/+4
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-4/+5
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-5/+4
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-4/+5
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* [AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon2014-10-011-24/+12
| | | | | | | | | | | | | | | | | | | | | The A64 instruction set includes a generic register syntax for accessing implementation-defined system registers. The syntax for these registers is: S<op0>_<op1>_<CRn>_<CRm>_<op2> The encoding space permitted for implementation-defined system registers is: op0 op1 CRn CRm op2 11 xxx 1x11 xxxx xxx The full encoding space can now be accessed: op0 op1 CRn CRm op2 xx xxx xxxx xxxx xxx This is useful to anyone needing to write assembly code supporting new system registers before the assembler has learned the official names for them. llvm-svn: 218753
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+901
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-1173/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* AArch64: add initial NEON supportTim Northover2013-08-011-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-1/+1
| | | | llvm-svn: 182680
* Fix undefined behavior in AArch64David Majnemer2013-04-111-7/+11
| | | | | | | | A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. llvm-svn: 179317
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-031-0/+216
| | | | llvm-svn: 178637
* AArch64: implement GICv3 system registersTim Northover2013-03-281-2/+70
| | | | llvm-svn: 178236
* Add icache prefetch operations to AArch64Tim Northover2013-02-061-0/+6
| | | | | | | This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. llvm-svn: 174495
* Fix formatting in AArch64 backend.Tim Northover2013-02-051-1/+2
| | | | | | | | | | | This should fix three purely whitespace issues: + 80 column violations. + Tab characters. + TableGen brace placement. No functional changes. llvm-svn: 174370
* Remove cyclic dependency in AArch64 librariesTim Northover2013-02-051-0/+812
This moves the bit twiddling and string fiddling functions required by other parts of the backend into a separate library. Previously they resided in AArch64Desc, which created a circular dependency between various components. llvm-svn: 174369
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