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* [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen2017-12-201-0/+20
| | | | | | | | | | | This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of of r320992, r320986, r320973, and r320970 by reverting https://reviews.llvm.org/rL321024. The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158, so this patch-series should be safe to resubmit. llvm-svn: 321163
* Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner2017-12-181-20/+0
| | | | | | | | | | This reverts changes r320992, r320986, r320973, and r320970. r320970 by itself breaks the test case, and the rest depend on it. Test case will land soon. llvm-svn: 321024
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-12-181-0/+20
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 320970
* Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen2017-11-291-20/+0
| | | | | | used by any instructions). llvm-svn: 319321
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-11-291-0/+20
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 319315
* [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing supportFlorian Hahn2017-11-071-0/+24
| | | | | | | | | | | | | | | | | | | | | Patch [3/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions. To summarise, this patch adds: * SVE register definitions * Methods to parse SVE register operands * Methods to print SVE register operands * RegKind SVEDataVector to distinguish it from other data types like scalar register or Neon vector. * k_SVEDataRegister and SVEDataRegOp to describe SVE registers (which will be extended by further patches with e.g. ElementWidth and the shift-extend type). Patch by Sander De Smalen. Reviewed by: rengolin Differential Revision: https://reviews.llvm.org/D39089 llvm-svn: 317590
* [AArch64] Fix for buildbots, unused functionSam Parker2017-08-181-3/+0
| | | | | | Removing function declaration, my previous commit broke the bots. llvm-svn: 311150
* [AArch64] Remove DecodeAuthLoadWritebackSam Parker2017-08-181-21/+0
| | | | | | | | | | | The BaseAuthLoad instruction class was incorrectly passing an empty constraint string to its parent, so I have corrected this. This makes the DecodeAuthLoadWriteback function redundant, so I've also removed it. Differential Revision: https://reviews.llvm.org/D36741 llvm-svn: 311148
* [AArch64] Enable ARMv8.3-A pointer authenticationSam Parker2017-08-111-0/+42
| | | | | | | | | Add assembler and disassembler support for the ARMv8.3-A pointer authentication instructions. Differential Revision: https://reviews.llvm.org/D36517 llvm-svn: 310709
* [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-251-107/+109
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309062
* Fix some more -Wimplicit-fallthrough warnings. NFCI.Simon Pilgrim2017-07-071-2/+2
| | | | llvm-svn: 307411
* [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-061-6/+3
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 291197
* Support: Remove MemoryObject and DataStreamer interfaces.Peter Collingbourne2016-11-021-1/+0
| | | | | | | | These interfaces are no longer used. Differential Revision: https://reviews.llvm.org/D26222 llvm-svn: 285774
* Move the global variables representing each Target behind accessor functionMehdi Amini2016-10-091-6/+6
| | | | | | | | This avoids "static initialization order fiasco" Differential Revision: https://reviews.llvm.org/D25412 llvm-svn: 283702
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-6/+6
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* Minor code cleanups. NFC.Junmo Park2016-07-151-2/+2
| | | | llvm-svn: 275637
* AArch64: TableGenerate system instruction operands.Tim Northover2016-07-051-6/+5
| | | | | | | | | | | | | | | | | | | | The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
* Untabify.NAKAMURA Takumi2016-06-201-1/+1
| | | | llvm-svn: 273129
* Update the AArch64ExternalSymbolizer to print literal strings as escaped stringsKevin Enderby2016-06-131-3/+5
| | | | | | | | so it is the same as the MCExternalSymbolizer. rdar://17349181 llvm-svn: 272588
* Remove autoconf supportChris Bieneman2016-01-261-16/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer2016-01-262-2/+2
| | | | | | No functional change, just moving code around. llvm-svn: 258818
* [AArch64] Add ARMv8.2-A UAO PSTATE bitOliver Stannard2015-11-261-1/+2
| | | | | | | | | | | | | ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR instructions to behave the same as LDR/STR with respect to execute-only pages at higher privilege levels. New variants of the MSR/MRS instructions are added to allow reading and writing this bit. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15020 llvm-svn: 254157
* [MC layer][AArch64] llvm-mc accepts 4-bit immediate values forAlexandros Lamprineas2015-10-051-0/+3
| | | | | | | | | "msr pan, #imm", while only 1-bit immediate values should be valid. Changed encoding and decoding for msr pstate instructions. Differential Revision: http://reviews.llvm.org/D13011 llvm-svn: 249313
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-151-4/+5
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* ↵Daniel Sanders2015-09-151-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and related. NFC. Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Thanks go to Pavel Labath for fixing LLDB for me. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247692
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-151-4/+5
| | | | | | LLDB needs to be updated in the same commit. llvm-svn: 247686
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-151-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247683
* Change the last few internal StringRef triples into Triple objects.Daniel Sanders2015-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | Summary: This concludes the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. At this point, the StringRef-form of GNU Triples should only be used in the public API (including IR serialization) and a couple objects that directly interact with the API (most notably the Module class). The next step is to replace these Triple objects with the TargetTuple object that will represent our authoratative/unambiguous internal equivalent to GNU Triples. Reviewers: rengolin Subscribers: llvm-commits, jholewinski, ted, rengolin Differential Revision: http://reviews.llvm.org/D10962 llvm-svn: 241472
* Fix "the the" in comments.Eric Christopher2015-06-191-1/+1
| | | | llvm-svn: 240112
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-022-1/+41
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-11/+11
| | | | llvm-svn: 238634
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-2/+2
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-132-50/+50
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [AArch64] Add v8.1a "Limited Ordering Regions" extensionVladimir Sukharev2015-04-161-0/+8
| | | | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8499 Patch by: Tom Coxon llvm-svn: 235105
* [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget ↵Vladimir Sukharev2015-04-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | features. In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available. This patch introduces refactoring, that will then allow to easily introduce: - v8.1-specific "pan" PState for PStateMapper (PAN extension) - v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions) Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8496 Patch by Tom Coxon llvm-svn: 235089
* unique_ptrify the RelInfo parameter to TargetRegistry::createMCSymbolizerDavid Blaikie2015-01-181-7/+5
| | | | llvm-svn: 226416
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-122-6/+3
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-102-14/+13
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [AArch64] Allow access to all system registers with MRS/MSR instructions.Tom Coxon2014-10-011-20/+4
| | | | | | | | | | | | | | | | | | | | | The A64 instruction set includes a generic register syntax for accessing implementation-defined system registers. The syntax for these registers is: S<op0>_<op1>_<CRn>_<CRm>_<op2> The encoding space permitted for implementation-defined system registers is: op0 op1 CRn CRm op2 11 xxx 1x11 xxxx xxx The full encoding space can now be accessed: op0 op1 CRn CRm op2 xx xxx xxxx xxxx xxx This is useful to anyone needing to write assembly code supporting new system registers before the assembler has learned the official names for them. llvm-svn: 218753
* [AArch64] Remove unnecessary whitespace. (Test commit)Tom Coxon2014-09-301-2/+2
| | | | llvm-svn: 218680
* Fix left shifts of negative integers in AArch64 InstPrinter/DisassemblerAlexey Samsonov2014-09-021-3/+3
| | | | | | | | | | | | | | | | | | | Summary: Left shift of negative integer is an undefined behavior, and is reported by UBSan. It's ok for imm values to be negative, so we can just replace left shifts with multiplications. Test Plan: check-llvm test suite Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D5132 llvm-svn: 216910
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-132-4/+4
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-2/+2
| | | | | | No functionality change. llvm-svn: 213938
* Update library dependencies.NAKAMURA Takumi2014-07-241-1/+1
| | | | llvm-svn: 213832
* Finish inverting the MC -> Object dependency.Rafael Espindola2014-07-231-1/+1
| | | | | | | There were still some disassembler bits in lib/MC, but their use of Object was only visible in the includes they used, not in the symbols. llvm-svn: 213808
* AArch64: remove "arm64_be" support in favour of "aarch64_be".Tim Northover2014-07-231-6/+2
| | | | | | | | | There really is no arm64_be: it was a useful fiction to test big-endian support while both backends existed in parallel, but now the only platform that uses the name (iOS) doesn't have a big-endian variant, let alone one called "arm64_be". llvm-svn: 213748
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-191-2/+1
| | | | | | the assert. llvm-svn: 211254
* Remove outdated CMake MSVC workaroundAlp Toker2014-06-081-7/+1
| | | | llvm-svn: 210421
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-247-0/+1911
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-244-1614/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
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