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* [AArch64] AsmParser should be case insensitive about accepting vector ↵Ranjeet Singh2015-06-081-1/+1
| | | | | | | | register names. Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-021-0/+85
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-15/+15
| | | | llvm-svn: 238634
* Reuse Loc variable. NFC.Chad Rosier2015-05-281-1/+1
| | | | llvm-svn: 238448
* Use operator<< instead of print in a few more places.Rafael Espindola2015-05-271-2/+2
| | | | llvm-svn: 238315
* [AArch64] Move AArch64TargetStreamer out of MCStreamer.hBenjamin Kramer2015-05-231-0/+1
| | | | | | It doesn't belong in the shared MC layer. NFC. llvm-svn: 238101
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-2/+2
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-64/+64
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* AArch64: add BFC alias for the BFI/BFM instructions.Tim Northover2015-04-301-2/+55
| | | | | | | | | Unlike 32-bit ARM, AArch64 can use wzr/xzr to implement this without the need for a separate instruction. rdar://18679590 llvm-svn: 236245
* [AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget ↵Vladimir Sukharev2015-04-161-5/+10
| | | | | | | | | | | | | | | | | | | | | | features. In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available. This patch introduces refactoring, that will then allow to easily introduce: - v8.1-specific "pan" PState for PStateMapper (PAN extension) - v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions) Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8496 Patch by Tom Coxon llvm-svn: 235089
* AArch64: disallow "fmov sD, #-0.0" during assembly.Tim Northover2015-04-071-3/+4
| | | | | | | | | | | | | We weren't checking the sign of the floating point immediate before translating it to "fmov sD, wzr". Similarly for D-regs. Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's not a blessed alias (and I don't think it should be since people expect writing sD to zero out the high lanes, and there's no dD equivalent). So an error it is. rdar://20455398 llvm-svn: 234372
* [AArch64] Don't store available subtarget features in ↵Vladimir Sukharev2015-03-271-4/+6
| | | | | | | | | | | | | | AArch64SysReg::SysRegMapper Subtarget features must not be a part of the target machine. So, they are now not being stored in SysRegMapper, but provided each time fromString()/toString() are called Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8655 llvm-svn: 233386
* [AArch64] Move initializations of AArch64NamedImmMapper out of void ↵Vladimir Sukharev2015-03-261-18/+48
| | | | | | | | | | | | | | | | AArch64Operand::print(...) class AArch64NamedImmMapper is to become dependent of SubTargetFeatures, while class AArch64Operand don't have access to the latter. So, AArch64NamedImmMapper constructor invocations are refactored away from methods of AArch64Operand. Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8579 llvm-svn: 233297
* Fix uses of reserved identifiers starting with an underscore followed by an ↵David Blaikie2015-03-161-7/+5
| | | | | | | | | uppercase letter This covers essentially all of llvm's headers and libs. One or two weird cases I wasn't sure were worth/appropriate to fix. llvm-svn: 232394
* Make static variables const if possible. Makes them go into a read-only section.Benjamin Kramer2015-03-081-29/+18
| | | | | | Or fold them into a initializer list which has the same effect. NFC. llvm-svn: 231598
* Fix some unnoticed/unwanted behavior change from r222319.Frederic Riss2015-02-041-1/+1
| | | | | | | | | The ARM assembler allows register alias redefinitions as long as it targets the same register. r222319 broke that. In the AArch64 case it would just produce a new warning, but in the ARM case it would error out on previously accepted assembler. llvm-svn: 228109
* AArch64: decode all MRS/MSR forms early to avoid saving FeatureBits.Tim Northover2015-01-221-42/+35
| | | | | | | | | | | | Currently, we're adding a uint64_t describing the current subtarget so that matching can check whether the specified register is valid. However, we want to move to a bitset for those bits (x86 has more than 64 of them). This can't live in a union so it's probably better to do the checks early (especially as there are only 3 of them). llvm-svn: 226841
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-1/+0
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* Remove StringMap::GetOrCreateValue in favor of StringMap::insertDavid Blaikie2014-11-191-1/+1
| | | | | | | | | | | | | | Having two ways to do this doesn't seem terribly helpful and consistently using the insert version (which we already has) seems like it'll make the code easier to understand to anyone working with standard data structures. (I also updated many references to the Entry's key and value to use first() and second instead of getKey{Data,Length,} and get/setValue - for similar consistency) Also removes the GetOrCreateValue functions so there's less surface area to StringMap to fix/improve/change/accommodate move semantics, etc. llvm-svn: 222319
* MCAsmParserExtension has a copy of the MCAsmParser. Use it.Rafael Espindola2014-11-111-10/+31
| | | | | | Base classes were storing a second copy. llvm-svn: 221667
* [AArch64] Add support for the .inst directive.Chad Rosier2014-10-221-0/+53
| | | | | | | | | | This has been implement using the MCTargetStreamer interface as is done in the ARM, Mips and PPC backends. Phabricator: http://reviews.llvm.org/D5891 PR20964 llvm-svn: 220422
* AArch64: allow constant expressions for shifted reg literalsJim Grosbach2014-09-231-6/+7
| | | | | | | | | | | | e.g., add w1, w2, w3, lsl #(2 - 1) This sort of thing comes up in pre-processed assembly playing macro games. Still validate that it's an assembly time constant. The early exit error check was just a bit overzealous and disallowed a left paren. rdar://18430542 llvm-svn: 218336
* Make isValidMCLOHType take unsigned instead of enum to avoid loading invalid ↵Alexey Samsonov2014-08-291-3/+2
| | | | | | enum values llvm-svn: 216797
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-5/+5
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-10/+10
| | | | | | No functionality change. llvm-svn: 213938
* AArch64: remove "arm64_be" support in favour of "aarch64_be".Tim Northover2014-07-231-3/+1
| | | | | | | | | There really is no arm64_be: it was a useful fiction to test big-endian support while both backends existed in parallel, but now the only platform that uses the name (iOS) doesn't have a big-endian variant, let alone one called "arm64_be". llvm-svn: 213748
* MC: support different sized constants in constant poolsDavid Peixotto2014-07-181-5/+16
| | | | | | | | | | | | | | | On AArch64 the pseudo instruction ldr <reg>, =... supports both 32-bit and 64-bit constants. Add support for 64 bit constants for the pools to support the pseudo instruction fully. Changes the AArch64 ldr-pseudo tests to use 32-bit registers and adds tests with 64-bit registers. Patch by Janne Grunau! Differential Revision: http://reviews.llvm.org/D4279 llvm-svn: 213387
* [AArch64] Cleanup AsmParser: no need to use dyn_cast + assert. cast does it ↵Arnaud A. de Grandmaison2014-07-171-41/+21
| | | | | | for us. llvm-svn: 213296
* [AArch64] Add logical alias instructions to MC AsmParserArnaud A. de Grandmaison2014-07-101-0/+33
| | | | | | | | | | | | | | | | This patch teaches the AsmParser to accept some logical+immediate instructions and convert them as shown: bic Rd, Rn, #imm -> and Rd, Rn, #~imm bics Rd, Rn, #imm -> ands Rd, Rn, #~imm orn Rd, Rn, #imm -> orr Rd, Rn, #~imm eon Rd, Rn, #imm -> eor Rd, Rn, #~imm Those instructions are an alternate syntax available to assembly coders, and are needed in order to support code already compiling with some other assemblers. For example, the bic construct is used by the linux kernel. llvm-svn: 212722
* Truncate the immediate in logical operation to the register widthArnaud A. de Grandmaison2014-07-081-2/+7
| | | | | | And continue to produce an error if the 32 most significant bits are not all ones or zeros. llvm-svn: 212520
* aarch64: support target-specific .req assembler directiveSaleem Abdulrasool2014-07-021-3/+96
| | | | | | | | | | Based on the support for .req on ARM. The aarch64 variant has to keep track if the alias register was a vector register (v0-31) or a general purpose or VFP/Advanced SIMD ([bhsdq]0-31) register. Patch by Janne Grunau! llvm-svn: 212161
* Resubmit commit r211533Weiming Zhao2014-06-241-1/+54
| | | | | | | "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Missed files are added in this commit. llvm-svn: 211605
* This reverts commit r211533 and r211539.Rafael Espindola2014-06-231-54/+1
| | | | | | | | | Revert "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Revert "Fix cmake build." It was missing a file. llvm-svn: 211540
* Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64Weiming Zhao2014-06-231-1/+54
| | | | | | | | | | | | | | | | | | | This patch is based on the changes from ARM target [1,2] Based on ARM doc [3], if the literal value can be loaded with a valid MOV, it can emit that instruction. This is implemented in this patch. [1] Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly Author: David Peixotto <dpeixott@codeaurora.org> commit b92cca222898d87bbc764fa22e805adb04ef7f13 (r200777) [2] Implement the ldr-pseudo opcode for ARM assembly Author: David Peixotto <dpeixott@codeaurora.org> commit 0fa193b08627927ccaa0804a34d80480894614b8 (r197708) [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CJAHAIBC.html Differential Revision: http://reviews.llvm.org/D4163 llvm-svn: 211533
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-191-2/+1
| | | | | | the assert. llvm-svn: 211254
* Condition codes AL and NV are invalid in the aliases that useArtyom Skrobov2014-06-101-1/+4
| | | | | | | | | | | | | | inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM). Matching aliases based on "immediate classes", when disassembling, wasn't previously supported, hence adding MCOperandPredicate into class Operand, and implementing the support for it in AsmWriterEmitter. The parsing for those aliases was already custom, so just adding the missing condition into AArch64AsmParser::parseCondCode. llvm-svn: 210528
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-135/+122
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* Add missing check when MatchInstructionImpl() reports failureArtyom Skrobov2014-05-291-0/+2
| | | | llvm-svn: 209802
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-244-0/+4091
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-244-2718/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-14/+14
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* PR18929:Stepan Dyatkovskiy2014-03-301-16/+22
| | | | | | | | According to ARM assembler language hash symbol is optional before immediates. For example, see here for more details: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473j/dom1359731154529.html llvm-svn: 205157
* [AArch64]Fix improper diagnostics about offset range of load/store instructions.Kevin Qin2014-03-041-2/+2
| | | | llvm-svn: 202775
* Add AArch64 big endian Target (aarch64_be)Christian Pirker2014-02-241-1/+2
| | | | llvm-svn: 202024
* [AArch64] Handle aliases of conditional branches without b.pred form.Chad Rosier2014-02-101-4/+25
| | | | llvm-svn: 201091
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-2/+2
| | | | llvm-svn: 200345
* [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point ↵Kevin Qin2014-01-201-0/+48
| | | | | | | | | | zero in asm parser. For FCMEQ, FCMGE, FCMGT, FCMLE and FCMLT, floating point zero will be printed as #0.0 instead of #0. To support the history codes using #0, we consider to let asm parser accept both #0.0 and #0. llvm-svn: 199621
* correct target directive handling error handlingSaleem Abdulrasool2014-01-131-5/+9
| | | | | | | | | | | | | | The target specific parser should return `false' if the target AsmParser handles the directive, and `true' if the generic parser should handle the directive. Many of the target specific directive handlers would `return Error' which does not follow these semantics. This change simply changes the target specific routines to conform to the semantis of the ParseDirective correctly. Conformance to the semantics improves diagnostics emitted for the invalid directives. X86 is taken as a sample to ensure that multiple diagnostics are not presented for a single error. llvm-svn: 199068
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