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* [AArch64] Enable post-RA MI scheduler.Chad Rosier2014-09-121-0/+3
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5278 Patch by Sanjin Sijaric! llvm-svn: 217693
* [AArch64] Enabled AA support for Cortex-A57.Chad Rosier2014-09-081-1/+1
| | | | llvm-svn: 217381
* [AArch64] Enabled AA support for Cortex-A53.Chad Rosier2014-09-081-0/+2
| | | | | | | Patch by Sanjin Sijaric <ssijaric@codeaurora.org>! Phabricator Review: http://reviews.llvm.org/D5103 llvm-svn: 217370
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [AArch64] Add a few isTarget* API to AArch64 Subtarget.Chad Rosier2014-08-061-1/+4
| | | | llvm-svn: 214977
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-5/+10
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Implement AArch64 TTI interface isAsCheapAsAMove.Jiangning Liu2014-07-291-0/+2
| | | | llvm-svn: 214159
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-1/+1
| | | | | | No functionality change. llvm-svn: 213938
* Move to a private function to initialize the subtarget dependenciesEric Christopher2014-06-111-2/+7
| | | | | | so that we can use initializer lists for the AArch64 Subtarget. llvm-svn: 210616
* Move AArch64TargetLowering to AArch64Subtarget.Eric Christopher2014-06-101-1/+6
| | | | | | | This currently necessitates a TargetMachine for the TargetLowering constructor and TLOF. llvm-svn: 210605
* Move AArch64InstrInfo to AArch64Subtarget.Eric Christopher2014-06-101-0/+3
| | | | llvm-svn: 210599
* Move AArch64SelectionDAGInfo down to the subtarget.Eric Christopher2014-06-101-0/+3
| | | | llvm-svn: 210557
* Remove the cached little endian variable. We can get it easily offEric Christopher2014-06-101-4/+1
| | | | | | of the DataLayout. llvm-svn: 210555
* Move DataLayout onto the AArch64 subtarget.Eric Christopher2014-06-101-1/+3
| | | | llvm-svn: 210552
* Move AArch64FrameLowering into the subtarget.Eric Christopher2014-06-101-1/+8
| | | | llvm-svn: 210549
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+110
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-89/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-1/+1
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [cleanup] Fix two headers where we included a standard library headerChandler Carruth2014-04-221-2/+1
| | | | | | after including the generated code from tablegen. llvm-svn: 206841
* This commit enables unaligned memory accesses of vector types on AArch64 ↵Jiangning Liu2014-04-181-0/+7
| | | | | | | | back end. This should boost vectorized code performance. Patched by Z. Zheng llvm-svn: 206557
* [AArch64] This is a work in progress to provide a machine descriptionChad Rosier2014-03-061-0/+5
| | | | | | | | | | | | | | | | | | | for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 203125
* Revert "[AArch64] This is a work in progress to provide a machine description"Chad Rosier2014-03-041-5/+0
| | | | | | This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc. llvm-svn: 202773
* [AArch64] This is a work in progress to provide a machine descriptionChad Rosier2014-03-031-0/+5
| | | | | | | | | | | | | | | | | | | for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 202767
* Add AArch64 big endian Target (aarch64_be)Christian Pirker2014-02-241-1/+7
| | | | llvm-svn: 202024
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-0/+1
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+0
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-0/+1
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* [AArch64] Make the use of FP instructions optional, but enabled by default.Amara Emerson2013-10-311-1/+11
| | | | | | | This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. llvm-svn: 193739
* AArch64: enable MISched by default.Tim Northover2013-10-091-0/+4
| | | | | | | | | | | | Substantial SelectionDAG scheduling is going away soon, and is interfering with Hao's attempts to implement LDn/STn instructions, so I say we make the leap first. There were a few reorderings (inevitably) which broke some tests. I tried to replace them with CHECK-DAG variants mostly, but some too complex for that to be useful and I just reordered them. llvm-svn: 192282
* Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-291-1/+1
| | | | | | if the target is iOS and Linux. llvm-svn: 189604
* AArch64: add initial NEON supportTim Northover2013-08-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
* Add AArch64 as an experimental target.Tim Northover2013-01-311-0/+54
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
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