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* [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-05-011-1/+64
| | | | | | NFC llvm-svn: 301841
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Predicate<> now has a field to indicate how often it must be recomputed. Currently, there are two frequencies, per-module (RecomputePerFunction==0) and per-function (RecomputePerFunction==1). Per-function predicates are currently recomputed more frequently than necessary since the only predicate in this category is cheap to test. Per-module predicates are now computed in getSubtargetImpl() while per-function predicates are computed in selectImpl(). Tablegen now manages the PredicateBitset internally. It should only be necessary to add the required includes. Also fixed a problem revealed by the test case where constrainSelectedInstRegOperands() would attempt to tie operands that BuildMI had already tied. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32491 llvm-svn: 301750
* AArch64: put nonlazybind special handling behind a flag for now.Tim Northover2017-04-171-1/+6
| | | | | | | | It's basically a terrible idea anyway but objc_msgSend gets emitted like that. We can decide on a better way to deal with it in the unlikely event that anyone actually uses it. llvm-svn: 300474
* AArch64: support nonlazybindTim Northover2017-04-171-0/+17
| | | | | | | | It's almost certainly not a good idea to actually use it in most cases (there's a pretty large code size overhead on AArch64), but we can't do those experiments until it's supported. llvm-svn: 300462
* [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsiaPetr Hosek2017-04-041-3/+3
| | | | | | | | | | | This mode is just like -mcmodel=small except that it moves the thread pointer from TPIDR_EL0 to TPIDR_EL1. Patch by Roland McGrath. Differential Revision: https://reviews.llvm.org/D31624 llvm-svn: 299462
* [AArch64] Vulcan is now ThunderXT99Joel Jones2017-03-071-3/+9
| | | | | | | | | | | | | | | | | Broadcom Vulcan is now Cavium ThunderX2T99. LLVM Bugzilla: http://bugs.llvm.org/show_bug.cgi?id=32113 Minor fixes for the alignments of loops and functions for ThunderX T81/T83/T88 (better performance). Patch was tested with SpecCPU2006. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D30510 llvm-svn: 297190
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-171-0/+8
| | | | | | | | | | | | | | This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 llvm-svn: 295475
* [AArch64] Reduce vector insert/extract cost for Falkor.Chad Rosier2017-01-061-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D28403 llvm-svn: 291254
* [AArch64] Set the max interleave factor for Falkor.Chad Rosier2016-11-221-1/+3
| | | | llvm-svn: 287642
* [AArch64] Add support for Qualcomm's Falkor CPU.Chad Rosier2016-11-151-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D26673 llvm-svn: 287036
* [AArch64] Adjust the cost model for Exynos M1.Evandro Menezes2016-10-251-1/+1
| | | | | | Modify the maximum jump table size. llvm-svn: 285106
* Set the vectorizer MaxInterleaveFactor for Exynos.Abderrazek Zaafrani2016-10-211-0/+1
| | | | llvm-svn: 284839
* GlobalISel: rename legalizer components to match others.Tim Northover2016-10-141-2/+2
| | | | | | | | | | The previous names were both misleading (the MachineLegalizer actually contained the info tables) and inconsistent with the selector & translator (in having a "Machine") prefix. This should make everything sensible again. The only functional change is the name of a couple of command-line options. llvm-svn: 284287
* AArch64Subtarget: Remove unused CPUString fieldMatthias Braun2016-10-031-3/+4
| | | | llvm-svn: 283142
* Add support to optionally limit the size of jump tables.Evandro Menezes2016-09-261-0/+1
| | | | | | | | | | | | | | | | | | | Many high-performance processors have a dedicated branch predictor for indirect branches, commonly used with jump tables. As sophisticated as such branch predictors are, they tend to have well defined limits beyond which their effectiveness is hampered or even nullified. One such limit is the number of possible destinations for a given indirect branches that such branch predictors can handle. This patch considers a limit that a target may set to the number of destination addresses in a jump table. Patch by: Evandro Menezes <e.menezes@samsung.com>, Aditya Kumar <aditya.k7@samsung.com>, Sebastian Pop <s.pop@samsung.com>. Differential revision: https://reviews.llvm.org/D21940 llvm-svn: 282412
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+5
| | | | | | | | And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
* GlobalISel: implement legalization pass, with just one transformation.Tim Northover2016-07-221-0/+5
| | | | | | | | | This adds the actual MachineLegalizeHelper to do the work and a trivial pass wrapper that legalizes all instructions in a MachineFunction. Currently the only transformation supported is splitting up a vector G_ADD into one acting on smaller vectors. llvm-svn: 276461
* Minor code cleanup. NFC.Junmo Park2016-07-061-1/+1
| | | | llvm-svn: 274702
* Target: Remove unused arguments from overrideSchedPolicy, NFCDuncan P. N. Exon Smith2016-07-011-2/+1
| | | | | | | | | | TargetSubtargetInfo::overrideSchedPolicy takes two MachineInstr* arguments (begin and end) that invite implicit conversions from MachineInstrBundleIterator. One option would be to change their type to an iterator, but since they don't seem to have been used since the API was added in 2010, I'm deleting the dead code. llvm-svn: 274304
* Delete unused includes. NFC.Rafael Espindola2016-06-301-1/+0
| | | | llvm-svn: 274225
* [AArch64] Add Broadcom Vulcan scheduling model.Pankaj Gode2016-06-301-1/+3
| | | | | | | | Adding scheduling model for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21728 llvm-svn: 274213
* Move shouldAssumeDSOLocal to Target.Rafael Espindola2016-06-271-2/+1
| | | | | | Should fix the shared library build. llvm-svn: 273958
* [Kryo] Enable loop prefetcher.Haicheng Wu2016-06-211-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D21535 llvm-svn: 273329
* [AArch64] Restore codegen for AArch64 Cortex-A72/A73 after NFCISilviu Baranga2016-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Code generation for Cortex-A72/Cortex-A73 was accidentally changed by r271555, which was a NFCI. The isCortexA57() predicate was not true for Cortex-A72/Cortex-A73 before r271555 (since it was checking the CPU string). Because Cortex-A72/Cortex-A73 inherit all features from Cortex-A57, all decisions previously guarded by isCortexA57() are now taken. This change restores the behaviour before r271555 by adding separate ProcA72/ProcA73, which have the required features to preserve code generation. Reviewers: kristof.beyls, aadg, mcrosier, rengolin Subscribers: mcrosier, llvm-commits, aemerson, t.p.northover, MatzeB, rengolin Differential Revision: http://reviews.llvm.org/D21182 llvm-svn: 273277
* [AARCH64] Add support for Broadcom VulcanPankaj Gode2016-06-201-0/+1
| | | | | | | | Adding core tuning support for new Broadcom Vulcan core (ARMv8.1A). Differential Revision: http://reviews.llvm.org/D21500 llvm-svn: 273148
* [AArch64] Add preferred alignments for Exynos M1Evandro Menezes2016-06-101-2/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D21203 llvm-svn: 272400
* AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun2016-06-021-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Testing for specific CPUs has a number of problems, better use subtarget features: - When some tweak is added for a specific CPU it is often desirable for the next version of that CPU as well, yet we often forget to add it. - It is hard to keep track of checks scattered around the target code; Declaring all target specifics together with the CPU in the tablegen file is a clear representation. - Subtarget features can be tweaked from the command line. To discourage people from using CPU checks in the future I removed the isCortexXX(), isCyclone(), ... functions. I added an getProcFamily() function for exceptional circumstances but made it clear in the comment that usage is discouraged. Reformat feature list in AArch64.td to have 1 feature per line in alphabetical order to simplify merging and sorting for out of tree tweaks. No functional change intended. Differential Revision: http://reviews.llvm.org/D20762 llvm-svn: 271555
* Delete AArch64II::MO_CONSTPOOL.Rafael Espindola2016-05-311-7/+2
| | | | | | | | A constant pool holding the address of a variable in equivalent to a got entry. It produces exactly the same instruction sequence as a got use and unlike a got use this is not uniqued by the linker. llvm-svn: 271311
* AArch64Subtarget: Use default member initializersMatthias Braun2016-05-271-6/+2
| | | | llvm-svn: 271057
* Use shouldAssumeDSOLocal on AArch64.Rafael Espindola2016-05-261-19/+6
| | | | | | This reduces code duplication and now AArch64 also handles PIE. llvm-svn: 270844
* Don't repeat name in comment and git-clang-format.Rafael Espindola2016-05-251-5/+5
| | | | llvm-svn: 270785
* Sort includes.Rafael Espindola2016-05-251-1/+1
| | | | llvm-svn: 270769
* [NFC] Header cleanupMehdi Amini2016-04-181-1/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [GlobalISel] Move GISelAccessor class into public headersTom Stellard2016-04-141-5/+5
| | | | | | | | | | Reviewers: qcolombet Subscribers: joker.eph, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D19120 llvm-svn: 266348
* [AArch64] Teach the subtarget how to get to the RegisterBankInfo.Quentin Colombet2016-04-061-4/+8
| | | | | | | | | | | Rework the access to GlobalISel APIs to contain how much of the APIs we need to access for the final executable to build when GlobalISel is not built. This prevents massive usage of ifdefs in various places. Now, all the GlobalISel ifdefs will be happing only in AArch64TargetMachine.cpp. llvm-svn: 265567
* [GlobalISel] Re-apply r260922-260923 with MSVC-friendly code.Quentin Colombet2016-02-161-1/+7
| | | | | | | | | Original message: Get rid of the ifdefs in TargetLowering. Introduce a new API used only by GlobalISel: CallLowering. This API will contain target hooks dedicated to call lowering. llvm-svn: 260998
* Reverting r260922-260923; they cause link failures with MSVC.Aaron Ballman2016-02-161-8/+1
| | | | | | | http://lab.llvm.org:8011/builders/lldb-x86-windows-msvc2015/builds/15436/steps/build/logs/stdio http://bb.pgr.jp/builders/msbuild-llvmclang-x64-msc18-DA/builds/961/steps/build_llvm/logs/stdio llvm-svn: 260972
* [GlobalISel] Get rid of the ifdefs in TargetLowering.Quentin Colombet2016-02-161-1/+8
| | | | | | | Introduce a new API used only by GlobalISel: CallLowering. This API will contain target hooks dedicated to call lowering. llvm-svn: 260922
* [AArch64] Add subtarget features for ARMv8.2-AOliver Stannard2015-11-261-5/+5
| | | | | | | | | | | | | | This adds subtarget features for ARMv8.2-A, which builds on (and requires the features from) ARMv8.1-A. Most assembler-visible features of ARMv8.2-A are system instructions, and are all required parts of the architecture, so just depend on the HasV8_2aOps subtarget feature. There is also one large, optional feature, which adds 16-bit floating point versions of all existing floating-point instructions (VFP and SIMD), this is represented by the FeatureFullFP16 subtarget feature. Differential Revision: http://reviews.llvm.org/D15013 llvm-svn: 254154
* AArch64: Default AArch64Subtarget::ReserveX18 to true on darwinJustin Bogner2015-11-131-2/+3
| | | | | | | | | | | Darwin reserves x18, so it's never ABI compliant to generate code that uses it. Set the default value based on the OS part of the triple rather than forcing front-ends to set the +reserve-x18 target feature in order to build correct code for Darwin. This will make r243310 redundant, so I'll revert that shortly. llvm-svn: 253102
* AArch64: add experimental support for address tagging.Tim Northover2015-11-101-0/+18
| | | | | | | | | | | | | AArch64 has the ability to use the top 8-bits of an "address" for extra information, with the memory subsystem automatically masking them off for loads and stores. When that's happening, we can sometimes skip masks on memory operations in the compiler. However, this requires the host OS and support stack to preserve those bits so it can't be enabled everywhere. In principle iOS 8.0 and above do take the required precautions and but we'll put it under a flag for now. llvm-svn: 252573
* AArch64: Disable the latency heuristicMatthias Braun2015-10-221-0/+5
| | | | | | | | | | | | It turned out not to improve any of our benchmarks but occasionally led to increased register pressure and spilling. Only enabling for the Cyclone CPU as the results on the cortex CPUs give mixed results. Differential Revision: http://reviews.llvm.org/D13708 llvm-svn: 251038
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-151-1/+1
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* ↵Daniel Sanders2015-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and related. NFC. Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Thanks go to Pavel Labath for fixing LLDB for me. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247692
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-151-1/+1
| | | | | | LLDB needs to be updated in the same commit. llvm-svn: 247686
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247683
* [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.Ahmed Bougacha2015-09-011-3/+3
| | | | | | | | | | This matches the ARM behavior. In both cases, the register is part of the optional Performance Monitors extension, so, add the feature, and enable it for the A-class processors we support. Differential Revision: http://reviews.llvm.org/D12425 llvm-svn: 246555
* [AArch64] Define subtarget feature strict-align.Akira Hatanaka2015-07-291-2/+2
| | | | | | | | | | This commit defines subtarget feature strict-align and uses it instead of cl::opt -aarch64-strict-align to decide whether strict alignment should be forced. rdar://problem/21529937 llvm-svn: 243516
* [AArch64] Define subtarget feature "reserve-x18", which is used to decideAkira Hatanaka2015-07-251-1/+2
| | | | | | | | | | | | | | | | | whether register x18 should be reserved. This change is needed because we cannot use a backend option to set cl::opt "aarch64-reserve-x18" when doing LTO. Out-of-tree projects currently using cl::opt option "-aarch64-reserve-x18" to reserve x18 should make changes to add subtarget feature "reserve-x18" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11463 llvm-svn: 243186
* Remove getDataLayout() from TargetSelectionDAGInfo (had no users)Mehdi Amini2015-07-091-2/+2
| | | | | | | | | | | | | | | | | | Summary: Remove empty subclass in the process. This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren, ted Differential Revision: http://reviews.llvm.org/D11045 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 241780
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