summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* [AArch64][RegisterBankInfo] Switch to TableGen'ed like PartialMapping.Quentin Colombet2016-09-231-20/+29
| | | | | | | | | Statically instanciate the most common PartialMappings. This should be closer to what the code would look like when TableGen support is added for GlobalISel. As a side effect, this should improve compile time. llvm-svn: 282215
* [RegisterBankInfo] Use array instead of SmallVector for BreakDown.Quentin Colombet2016-09-231-5/+12
| | | | | | | | | | | | | This is another step toward TableGen'ed like structures. The BreakDown of the mapping of the value will be statically computed by TableGen, thus we only have to point to the right entry in the table instead of dynamically allocate the mapping for each instruction. We still support the dynamic allocation through a factory of PartialMapping to ease the bring-up of the targets while the TableGen backend is not available. llvm-svn: 282213
* [RegisterBankInfo] Move to statically allocated RegisterBank.Quentin Colombet2016-09-221-1/+19
| | | | | | | | | | | | This commit is basically the first step toward what will RegisterBankInfo look when it gets TableGen'ed. It introduces a XXXGenRegisterBankInfo.def file that is what TableGen will issue at some point. Moreover, the RegBanks field in RegisterBankInfo changed to reflect the static (compile time) aspect of the information. llvm-svn: 282131
* [AArch64][GlobalISel] Add default regbank mapping for int<>FP.Ahmed Bougacha2016-09-161-0/+10
| | | | llvm-svn: 281739
* [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.Ahmed Bougacha2016-09-161-0/+10
| | | | llvm-svn: 281738
* [AArch64][GlobalISel] Add default regbank mapping for FP ops.Ahmed Bougacha2016-09-161-1/+18
| | | | | | These should have all their operands - even scalars - go on FPR. llvm-svn: 281737
* [AArch64][GlobalISel] Add default regbank mappings for mixed-type ops.Ahmed Bougacha2016-09-161-18/+36
| | | | | | | | We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
* [AArch64][GlobalISel] Use the generic DefaultMapping as the default.Ahmed Bougacha2016-09-161-2/+1
| | | | | | | This lets generic logic handle the common case, instead of having to implement applyMappingImpl for each instruction. llvm-svn: 281720
* GlobalISel: remove "unsized" LLTTim Northover2016-09-151-1/+1
| | | | | | | | It was only really there as a sentinel when instructions had to have precisely one type. Now that registers are typed, each register really has to have a type that is sized. llvm-svn: 281599
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-091-1/+4
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-201-0/+25
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* [AArch64][RegisterBankInfo] G_OR are fine on either GPR or FPR.Quentin Colombet2016-06-081-0/+55
| | | | | | | | | | Teach AArch64RegisterBankInfo that G_OR can be mapped on either GPR or FPR for 64-bit or 32-bit values. Add test cases demonstrating how this information is used to coalesce a computation on a single register bank. llvm-svn: 272170
* [AArch64][RegisterBankInfo] Use the generic implementation of copyCost.Quentin Colombet2016-06-081-1/+2
| | | | | | Long term we may want to give high cost at FPR to/from GPR copies. llvm-svn: 272086
* [RegisterBankInfo] Add a size argument for the cost of copy.Quentin Colombet2016-06-081-1/+2
| | | | | | | The cost of a copy may be different based on how many bits we have to copy around. E.g., a 8-bit copy may be different than a 32-bit copy. llvm-svn: 272084
* [RegisterBankInfo] Change the API for the verify methods.Quentin Colombet2016-04-211-1/+1
| | | | | | | Return bool instead of void so that it is natural to put the calls into asserts. llvm-svn: 267033
* [AArch64] Fix a typo in the register class to register bank mapping.Quentin Colombet2016-04-071-1/+1
| | | | | | For GPR family we want the GPR register bank, not FPR! llvm-svn: 265743
* [RegisterBank] Rename RegisterBank::contains into RegisterBank::covers.Quentin Colombet2016-04-071-4/+4
| | | | llvm-svn: 265695
* [AArch64] Teach RegisterBankInfo about the CC register bank.Quentin Colombet2016-04-071-0/+11
| | | | | | We need to cover each register class with a register bank. llvm-svn: 265629
* [AArch64] Teach RegisterBankInfo about the mapping of register classesQuentin Colombet2016-04-071-0/+35
| | | | | | on register banks. llvm-svn: 265626
* Put quotes around #error string.James Y Knight2016-04-061-1/+1
| | | | | | | GCC reports "missing terminating ' character", even when it's being skipped by preprocessing. llvm-svn: 265590
* [AArch64] Change the CMake to avoid to build GlobalISel related APIsQuentin Colombet2016-04-061-10/+2
| | | | | | | | | | when GISel is not built. The positive side effects are: - We do not have to define dummy implementation - We do not have to do weird gymnastic to avoid like issues (like missing constructor or vtable for the base classes) llvm-svn: 265570
* [AArch64] Use the default constructor of RegisterBankInfo when GlobalISel is ↵Quentin Colombet2016-04-061-1/+1
| | | | | | | | | not built. This will avoid link-time error as the defautl constructor of RegisterBankInfo is the only one available when GlobalISel is not built. llvm-svn: 265549
* [AArch64] Initial implementation of the targeting of the register bank ↵Quentin Colombet2016-04-051-0/+73
information. llvm-svn: 265489
OpenPOWER on IntegriCloud