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path: root/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
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* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* Untabify.NAKAMURA Takumi2017-08-281-2/+2
| | | | llvm-svn: 311875
* [AArch64] Tie source and destination operands for AESMC/AESIMC. Florian Hahn2017-07-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Most CPUs implementing AES fusion require instruction pairs of the form AESE Vn, _ AESMC Vn, Vn and AESD Vn, _ AESIMC Vn, Vn The constraint is added to AES(I)MC instructions which use the result of an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which constraint source and destination registers to be the same. A nice side effect of this change is that now all possible pairs are scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll test case. I had to update aes_load_store. The version I added initially was very reduced and with the new constraint, AESE/AESMC could not be scheduled back-to-back. I updated the test to be more realistic and still expose the same scheduling problem as the initial test case. Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga Reviewed By: t.p.northover, evandro Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35299 llvm-svn: 309495
* [AArch64] Fix order of checks in shouldScheduleAdjacent.Florian Hahn2017-06-191-2/+2
| | | | | | | We need to check the opcode of FirstMI before accessing the operands. This caused a buildbot failure during bootstrapping on AArch64. llvm-svn: 305694
* Recommit rL305677: [CodeGen] Add generic MacroFusion passFlorian Hahn2017-06-191-152/+31
| | | | | | | | | | | | | Use llvm::make_unique to avoid ambiguity with MSVC. This patch adds a generic MacroFusion pass, that is used on X86 and AArch64, which both define target-specific shouldScheduleAdjacent functions. This generic pass should make it easier for other targets to implement macro fusion and I intend to add macro fusion for ARM shortly. Differential Revision: https://reviews.llvm.org/D34144 llvm-svn: 305690
* Revert r305677 [CodeGen] Add generic MacroFusion pass.Florian Hahn2017-06-191-31/+152
| | | | | | This causes Windows buildbot failures do an ambiguous call. llvm-svn: 305681
* [CodeGen] Add generic MacroFusion pass.Florian Hahn2017-06-191-152/+31
| | | | | | | | | | | | | | | | | | Summary: This patch adds a generic MacroFusion pass, that is used on X86 and AArch64, which both define target-specific shouldScheduleAdjacent functions. This generic pass should make it easier for other targets to implement macro fusion and I intend to add macro fusion for ARM shortly. Reviewers: craig.topper, evandro, t.p.northover, atrick, MatzeB Reviewed By: MatzeB Subscribers: atrick, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34144 llvm-svn: 305677
* [AArch64] Make instruction fusion more aggressive. Florian Hahn2017-05-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch makes instruction fusion more aggressive by * adding artificial edges between the successors of FirstSU and SecondSU, similar to BaseMemOpClusterMutation::clusterNeighboringMemOps. * updating PostGenericScheduler::tryCandidate to keep clusters together, similar to GenericScheduler::tryCandidate. This change increases the number of AES instruction pairs generated on Cortex-A57 and Cortex-A72. This doesn't change code at all in most benchmarks or general code, but we've seen improvement on kernels using AESE/AESMC and AESD/AESIMC. Reviewers: evandro, kristof.beyls, t.p.northover, silviu.baranga, atrick, rengolin, MatzeB Reviewed By: evandro Subscribers: aemerson, rengolin, MatzeB, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33230 llvm-svn: 303618
* [AArch64] Simplify MacroFusionEvandro Menezes2017-04-111-79/+89
| | | | | | | | | | | | This patch assumes that the dependents to be scanned for the ExitSU are its predecessors; otherwise, the successors of the instr are scanned. Furthermore, sometimes the ExitSU was being fused twice, since it may be fused once when scanning the successors from the beginning of the BB and then again when scanning the predecessors of ExitSU. Thus, when scanning the successors of an instr, skip the ExitSU. llvm-svn: 299974
* [AArch64, X86] Additional debug information for MacroFusionEvandro Menezes2017-03-101-5/+13
| | | | | | | | In order to make it easier to parse information about the performance of MacroFusion, this patch adds the function and the instruction names to the debug output of this pass. llvm-svn: 297504
* [AArch64, X86] Add statistics for the MacroFusion passEvandro Menezes2017-02-211-0/+4
| | | | llvm-svn: 295777
* [AArch64, X86] Guard against both instrs being wild cardsEvandro Menezes2017-02-211-4/+5
| | | | | | If both instrs are wild cards, the result can be a crash. llvm-svn: 295776
* [AArch64] Prefer static_cast<> to C-style cast. NFCI.Davide Italiano2017-02-191-2/+4
| | | | llvm-svn: 295615
* [AArch64] Fix enumeral/non-enumeral conditional expression warning.Simon Pilgrim2017-02-181-4/+4
| | | | | | gcc only allows you to mix enums / ints if they have the same signedness. llvm-svn: 295577
* *MacroFusion.cpp: Suppress warnings to eliminate \param(s). [-Wdocumentation]NAKAMURA Takumi2017-02-011-2/+2
| | | | llvm-svn: 293744
* [AArch64] Add new target feature to fuse literal generationEvandro Menezes2017-02-011-0/+25
| | | | | | | | | This feature enables the fusion of such operations on Cortex A57, as recommended in its Software Optimisation Guide, sections 4.14 and 4.15. Differential revision: https://reviews.llvm.org/D28698 llvm-svn: 293739
* [AArch64] Add new subtarget feature to fuse AES crypto operationsEvandro Menezes2017-02-011-0/+13
| | | | | | | | | | This feature enables the fusion of such operations on Cortex A57, as recommended in its Software Optimisation Guide, section 4.13, and on Exynos M1. Differential revision: https://reviews.llvm.org/D28491 llvm-svn: 293738
* [CodeGen] Move MacroFusion to the targetEvandro Menezes2017-02-011-0/+209
This patch moves the class for scheduling adjacent instructions, MacroFusion, to the target. In AArch64, it also expands the fusion to all instructions pairs in a scheduling block, beyond just among the predecessors of the branch at the end. Differential revision: https://reviews.llvm.org/D28489 llvm-svn: 293737
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