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path: root/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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* [AArch64] Register (existing) AArch64LoadStoreOpt pass with LLVM pass manager.Chad Rosier2015-08-051-2/+13
| | | | | | | | | Summary: Among other things, this allows -print-after-all/-print-before-all to dump IR around this pass. This is the AArch64 version of r243052. llvm-svn: 244041
* Update comment. NFC.Chad Rosier2015-08-051-2/+2
| | | | llvm-svn: 244038
* Convert some AArch64 code to foreach loops. NFC.Pete Cooper2015-08-031-3/+2
| | | | | | | Also converted a cast<> to dyn_cast while i was working on the same line of code. llvm-svn: 243894
* Simplify switch as all cases other than default return true. NFC.Chad Rosier2015-07-221-10/+0
| | | | llvm-svn: 242922
* Follow up to r242810. NFC.Chad Rosier2015-07-211-1/+1
| | | | llvm-svn: 242812
* [AArch64] Simplify the passing of arguments. NFC.Chad Rosier2015-07-211-23/+37
| | | | | | This is setup for future work planned for the AArch64 Load/Store Opt pass. llvm-svn: 242810
* [AArch64] Remove an overly conservative check when generating store pairs.Chad Rosier2015-06-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Store instructions do not modify register values and therefore it's safe to form a store pair even if the source register has been read in between the two store instructions. Previously, the read of w1 (see below) prevented the formation of a stp. str w0, [x2] ldr w8, [x2, #8] add w0, w8, w1 str w1, [x2, #4] ret We now generate the following code. stp w0, w1, [x2] ldr w8, [x2, #8] add w0, w8, w1 ret All correctness tests with -Ofast on A57 with Spec200x and EEMBC pass. Performance results for SPEC2K were within noise. llvm-svn: 239432
* [AArch64] Enhance the load/store optimizer with target-specific alias analysis.Chad Rosier2015-05-211-20/+51
| | | | | Phabricator: http://reviews.llvm.org/D9863 llvm-svn: 237963
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-181-2/+2
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* [AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.Quentin Colombet2015-03-061-11/+116
| | | | | | | | | | | Teach the load store optimizer how to sign extend a result of a load pair when it helps creating more pairs. The rational is that loads are more expensive than sign extensions, so if we gather some in one instruction this is better! <rdar://problem/20072968> llvm-svn: 231527
* Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.Eric Christopher2015-01-281-4/+2
| | | | llvm-svn: 227293
* [AArch64][LoadStoreOptimizer] Form LDPSW when possible.Quentin Colombet2015-01-241-1/+15
| | | | | | | | | This patch adds the missing LD[U]RSW variants to the load store optimizer, so that we generate LDPSW when possible. <rdar://problem/19583480> llvm-svn: 226978
* Add missing closing namespace comment.Jim Grosbach2014-08-111-1/+1
| | | | llvm-svn: 215402
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Run sort_includes.py on the AArch64 backend.Benjamin Kramer2014-07-251-4/+4
| | | | | | No functionality change. llvm-svn: 213938
* [AArch64] clang-format the load/store optimizer.Tilmann Scheller2014-06-041-16/+25
| | | | | | No change in functionality. llvm-svn: 210182
* [AArch64] Fix some LLVM Coding Standards violations in the load/store optimizer.Tilmann Scheller2014-06-041-19/+19
| | | | | | | | Variable names should start with an upper case letter. No change in functionality. llvm-svn: 210181
* [AArch64] Fix typo in load/store optimizer.Tilmann Scheller2014-06-031-1/+1
| | | | llvm-svn: 210114
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+942
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
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